Digital electronics

Contents
1 NUMERATION SYSTEMS 1
1.1 Numbers and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Systems of numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Decimal versus binary numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Octal and hexadecimal numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Octal and hexadecimal to decimal conversion . . . . . . . . . . . . . . . . . . . . . . 12
1.6 Conversion from decimal numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 BINARY ARITHMETIC 19
2.1 Numbers versus numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Binary addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Negative binary numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Over°ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Bit groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 LOGIC GATES 29
3.1 Digital signals and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 The NOT gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 The "bu®er" gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Multiple-input gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 TTL NAND and AND gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6 TTL NOR and OR gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.7 CMOS gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.8 Special-output gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.9 Gate universality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.10 Logic signal voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.11 DIP gate packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.12 Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4 SWITCHES 103
4.1 Switch types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2 Switch contact design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3 Contact "normal" state and make/break sequence . . . . . . . . . . . . . . . . . . . 111
iii
iv CONTENTS
4.4 Contact "bounce" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5 ELECTROMECHANICAL RELAYS 119
5.1 Relay construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2 Contactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3 Time-delay relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.4 Protective relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.5 Solid-state relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6 LADDER LOGIC 135
6.1 "Ladder" diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2 Digital logic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3 Permissive and interlock circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.4 Motor control circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.5 Fail-safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.6 Programmable logic controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.7 Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
7 BOOLEAN ALGEBRA 173
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.2 Boolean arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.3 Boolean algebraic identities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.4 Boolean algebraic properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.5 Boolean rules for simpli¯cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.6 Circuit simpli¯cation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.7 The Exclusive-OR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.8 DeMorgan's Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.9 Converting truth tables into Boolean expressions . . . . . . . . . . . . . . . . . . . . 200
8 KARNAUGH MAPPING 219
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.2 Venn diagrams and sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3 Boolean Relationships on Venn Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 223
8.4 Making a Venn diagram look like a Karnaugh map . . . . . . . . . . . . . . . . . . . 228
8.5 Karnaugh maps, truth tables, and Boolean expressions . . . . . . . . . . . . . . . . . 231
8.6 Logic simpli¯cation with Karnaugh maps . . . . . . . . . . . . . . . . . . . . . . . . 238
8.7 Larger 4-variable Karnaugh maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
8.8 Minterm vs maxterm solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8.9 § (sum) and ¦ (product) notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
8.10 Don't care cells in the Karnaugh map . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.11 Larger 5 & 6-variable Karnaugh maps . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9 COMBINATIONAL LOGIC FUNCTIONS 273
CONTENTS v
10 MULTIVIBRATORS 275
10.1 Digital logic with feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
10.2 The S-R latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
10.3 The gated S-R latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
10.4 The D latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
10.5 Edge-triggered latches: Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.6 The J-K °ip-°op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.7 Asynchronous °ip-°op inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.8 Monostable multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
11 COUNTERS 299
11.1 Binary count sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
11.2 Asynchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
11.3 Synchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
11.4 Counter modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
12 SHIFT REGISTERS 315
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
12.2 shift register, serial-in/serial-out shift . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
12.3 shift register, parallel-in, serial-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
12.4 Serial-in, parallel-out shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
12.5 Parallel-in, parallel-out, universal shift register . . . . . . . . . . . . . . . . . . . . . 347
12.6 Ring counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
13 DIGITAL-ANALOG CONVERSION 371
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
13.2 The R/2nR DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
13.3 The R/2R DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
13.4 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
13.5 Digital ramp ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
13.6 Successive approximation ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
13.7 Tracking ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
13.8 Slope (integrating) ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
13.9 Delta-Sigma (¢§) ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
13.10Practical considerations of ADC circuits . . . . . . . . . . . . . . . . . . . . . . . . . 391
14 DIGITAL COMMUNICATION 397
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.2 Networks and busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
14.3 Data °ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
14.4 Electrical signal types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
14.5 Optical data communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
14.6 Network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
14.7 Network protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.8 Practical considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
vi CONTENTS
15 DIGITAL STORAGE (MEMORY) 419
15.1 Why digital? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.2 Digital memory terms and concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
15.3 Modern nonmechanical memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
15.4 Historical, nonmechanical memory technologies . . . . . . . . . . . . . . . . . . . . . 424
15.5 Read-only memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
15.6 Memory with moving parts: "Drives" . . . . . . . . . . . . . . . . . . . . . . . . . . 430
16 PRINCIPLES OF DIGITAL COMPUTING 433
16.1 A binary adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
16.2 Look-up tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
16.3 Finite-state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
16.4 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.5 Microprocessor programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
A-1 ABOUT THIS BOOK 449
A-2 CONTRIBUTOR LIST 453
A-3 DESIGN SCIENCE LICENSE 457
Chapter 1
NUMERATION SYSTEMS
Contents
1.1 Numbers and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Systems of numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Decimal versus binary numeration . . . . . . . . . . . . . . . . . . . . . 8
1.4 Octal and hexadecimal numeration . . . . . . . . . . . . . . . . . . . . . 10
1.5 Octal and hexadecimal to decimal conversion . . . . . . . . . . . . . . 12
1.6 Conversion from decimal numeration . . . . . . . . . . . . . . . . . . . 13
"There are three types of people: those who can count, and those who can't."
Anonymous
1.1 Numbers and symbols
The expression of numerical quantities is something we tend to take for granted. This is both a
good and a bad thing in the study of electronics. It is good, in that we're accustomed to the use
and manipulation of numbers for the many calculations used in analyzing electronic circuits. On
the other hand, the particular system of notation we've been taught from grade school onward is
not the system used internally in modern electronic computing devices, and learning any di®erent
system of notation requires some re-examination of deeply ingrained assumptions.
First, we have to distinguish the di®erence between numbers and the symbols we use to represent
numbers. A number is a mathematical quantity, usually correlated in electronics to a physical
quantity such as voltage, current, or resistance. There are many di®erent types of numbers. Here
are just a few types, for example:
WHOLE NUMBERS:
1, 2, 3, 4, 5, 6, 7, 8, 9 . . .
INTEGERS:
-4, -3, -2, -1, 0, 1, 2, 3, 4 . . .
1
2 CHAPTER 1. NUMERATION SYSTEMS
IRRATIONAL NUMBERS:
¼ (approx. 3.1415927), e (approx. 2.718281828),
square root of any prime
REAL NUMBERS:
(All one-dimensional numerical values, negative and positive,
including zero, whole, integer, and irrational numbers)
COMPLEX NUMBERS:
3 - j4 , 34.5 6 20o
Di®erent types of numbers ¯nd di®erent application in the physical world. Whole numbers
work well for counting discrete objects, such as the number of resistors in a circuit. Integers are
needed when negative equivalents of whole numbers are required. Irrational numbers are numbers
that cannot be exactly expressed as the ratio of two integers, and the ratio of a perfect circle's
circumference to its diameter (¼) is a good physical example of this. The non-integer quantities of
voltage, current, and resistance that we're used to dealing with in DC circuits can be expressed as
real numbers, in either fractional or decimal form. For AC circuit analysis, however, real numbers
fail to capture the dual essence of magnitude and phase angle, and so we turn to the use of complex
numbers in either rectangular or polar form.
If we are to use numbers to understand processes in the physical world, make scienti¯c predictions,
or balance our checkbooks, we must have a way of symbolically denoting them. In other words, we
may know how much money we have in our checking account, but to keep record of it we need to
have some system worked out to symbolize that quantity on paper, or in some other kind of form
for record-keeping and tracking. There are two basic ways we can do this: analog and digital. With
analog representation, the quantity is symbolized in a way that is in¯nitely divisible. With digital
representation, the quantity is symbolized in a way that is discretely packaged.
You're probably already familiar with an analog representation of money, and didn't realize it
for what it was. Have you ever seen a fund-raising poster made with a picture of a thermometer on
it, where the height of the red column indicated the amount of money collected for the cause? The
more money collected, the taller the column of red ink on the poster.
1.1. NUMBERS AND SYMBOLS 3
$50,000
$0
$10,000
$20,000
$30,000
$40,000
An analog representation
of a numerical quantity
This is an example of an analog representation of a number. There is no real limit to how ¯nely
divided the height of that column can be made to symbolize the amount of money in the account.
Changing the height of that column is something that can be done without changing the essential
nature of what it is. Length is a physical quantity that can be divided as small as you would like,
with no practical limit. The slide rule is a mechanical device that uses the very same physical
quantity { length { to represent numbers, and to help perform arithmetical operations with two or
more numbers at a time. It, too, is an analog device.
On the other hand, a digital representation of that same monetary ¯gure, written with standard
symbols (sometimes called ciphers), looks like this:
$35,955.38
Unlike the "thermometer" poster with its red column, those symbolic characters above cannot
be ¯nely divided: that particular combination of ciphers stand for one quantity and one quantity
only. If more money is added to the account (+ $40.12), di®erent symbols must be used to represent
the new balance ($35,995.50), or at least the same symbols arranged in di®erent patterns. This is an
example of digital representation. The counterpart to the slide rule (analog) is also a digital device:
the abacus, with beads that are moved back and forth on rods to symbolize numerical quantities:
4 CHAPTER 1. NUMERATION SYSTEMS
Numerical quantities are represented by
the positioning of the slide.
Slide
Slide rule (an analog device)
Numerical quantities are represented by
Abacus (a digital device)
the discrete positions of the beads.
Lets contrast these two methods of numerical representation:
ANALOG DIGITAL
------------------------------------------------------------------
Intuitively understood ----------- Requires training to interpret
Infinitely divisible -------------- Discrete
Prone to errors of precision ------ Absolute precision
Interpretation of numerical symbols is something we tend to take for granted, because it has been
taught to us for many years. However, if you were to try to communicate a quantity of something to
a person ignorant of decimal numerals, that person could still understand the simple thermometer
chart!
The in¯nitely divisible vs. discrete and precision comparisons are really °ip-sides of the same
coin. The fact that digital representation is composed of individual, discrete symbols (decimal digits
and abacus beads) necessarily means that it will be able to symbolize quantities in precise steps. On
the other hand, an analog representation (such as a slide rule's length) is not composed of individual
steps, but rather a continuous range of motion. The ability for a slide rule to characterize a numerical
quantity to in¯nite resolution is a trade-o® for imprecision. If a slide rule is bumped, an error will
be introduced into the representation of the number that was "entered" into it. However, an abacus
1.1. NUMBERS AND SYMBOLS 5
must be bumped much harder before its beads are completely dislodged from their places (su±cient
to represent a di®erent number).
Please don't misunderstand this di®erence in precision by thinking that digital representation
is necessarily more accurate than analog. Just because a clock is digital doesn't mean that it will
always read time more accurately than an analog clock, it just means that the interpretation of its
display is less ambiguous.
Divisibility of analog versus digital representation can be further illuminated by talking about the
representation of irrational numbers. Numbers such as ¼ are called irrational, because they cannot
be exactly expressed as the fraction of integers, or whole numbers. Although you might have learned
in the past that the fraction 22/7 can be used for ¼ in calculations, this is just an approximation.
The actual number "pi" cannot be exactly expressed by any ¯nite, or limited, number of decimal
places. The digits of ¼ go on forever:
3.1415926535897932384 . . . . .
It is possible, at least theoretically, to set a slide rule (or even a thermometer column) so as
to perfectly represent the number ¼, because analog symbols have no minimum limit to the degree
that they can be increased or decreased. If my slide rule shows a ¯gure of 3.141593 instead of
3.141592654, I can bump the slide just a bit more (or less) to get it closer yet. However, with digital
representation, such as with an abacus, I would need additional rods (place holders, or digits) to
represent ¼ to further degrees of precision. An abacus with 10 rods simply cannot represent any
more than 10 digits worth of the number ¼, no matter how I set the beads. To perfectly represent
¼, an abacus would have to have an in¯nite number of beads and rods! The tradeo®, of course, is
the practical limitation to adjusting, and reading, analog symbols. Practically speaking, one cannot
read a slide rule's scale to the 10th digit of precision, because the marks on the scale are too coarse
and human vision is too limited. An abacus, on the other hand, can be set and read with no
interpretational errors at all.
Furthermore, analog symbols require some kind of standard by which they can be compared for
precise interpretation. Slide rules have markings printed along the length of the slides to translate
length into standard quantities. Even the thermometer chart has numerals written along its height
to show how much money (in dollars) the red column represents for any given amount of height.
Imagine if we all tried to communicate simple numbers to each other by spacing our hands apart
varying distances. The number 1 might be signi¯ed by holding our hands 1 inch apart, the number
2 with 2 inches, and so on. If someone held their hands 17 inches apart to represent the number 17,
would everyone around them be able to immediately and accurately interpret that distance as 17?
Probably not. Some would guess short (15 or 16) and some would guess long (18 or 19). Of course,
¯shermen who brag about their catches don't mind overestimations in quantity!
Perhaps this is why people have generally settled upon digital symbols for representing numbers,
especially whole numbers and integers, which ¯nd the most application in everyday life. Using the
¯ngers on our hands, we have a ready means of symbolizing integers from 0 to 10. We can make
hash marks on paper, wood, or stone to represent the same quantities quite easily:
5 + 5 + 3 = 13
For large numbers, though, the "hash mark" numeration system is too ine±cient.
6 CHAPTER 1. NUMERATION SYSTEMS
1.2 Systems of numeration
The Romans devised a system that was a substantial improvement over hash marks, because it used
a variety of symbols (or ciphers) to represent increasingly large quantities. The notation for 1 is the
capital letter I. The notation for 5 is the capital letter V. Other ciphers possess increasing values:
X = 10
L = 50
C = 100
D = 500
M = 1000
If a cipher is accompanied by another cipher of equal or lesser value to the immediate right of it,
with no ciphers greater than that other cipher to the right of that other cipher, that other cipher's
value is added to the total quantity. Thus, VIII symbolizes the number 8, and CLVII symbolizes
the number 157. On the other hand, if a cipher is accompanied by another cipher of lesser value to
the immediate left, that other cipher's value is subtracted from the ¯rst. Therefore, IV symbolizes
the number 4 (V minus I), and CM symbolizes the number 900 (M minus C). You might have noticed
that ending credit sequences for most motion pictures contain a notice for the date of production,
in Roman numerals. For the year 1987, it would read: MCMLXXXVII. Let's break this numeral down
into its constituent parts, from left to right:
M = 1000
+
CM = 900
+
L = 50
+
XXX = 30
+
V = 5
+
II = 2
Aren't you glad we don't use this system of numeration? Large numbers are very di±cult to
denote this way, and the left vs. right / subtraction vs. addition of values can be very confusing,
too. Another major problem with this system is that there is no provision for representing the
number zero or negative numbers, both very important concepts in mathematics. Roman culture,
however, was more pragmatic with respect to mathematics than most, choosing only to develop their
numeration system as far as it was necessary for use in daily life.
We owe one of the most important ideas in numeration to the ancient Babylonians, who were
the ¯rst (as far as we know) to develop the concept of cipher position, or place value, in representing
larger numbers. Instead of inventing new ciphers to represent larger numbers, as the Romans did,
they re-used the same ciphers, placing them in di®erent positions from right to left. Our own decimal
numeration system uses this concept, with only ten ciphers (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9) used in
"weighted" positions to represent very large and very small numbers.
1.2. SYSTEMS OF NUMERATION 7
Each cipher represents an integer quantity, and each place from right to left in the notation
represents a multiplying constant, or weight, for each integer quantity. For example, if we see the
decimal notation "1206", we known that this may be broken down into its constituent weight-
products as such:
1206 = 1000 + 200 + 6
1206 = (1 x 1000) + (2 x 100) + (0 x 10) + (6 x 1)
Each cipher is called a digit in the decimal numeration system, and each weight, or place value, is
ten times that of the one to the immediate right. So, we have a ones place, a tens place, a hundreds
place, a thousands place, and so on, working from right to left.
Right about now, you're probably wondering why I'm laboring to describe the obvious. Who
needs to be told how decimal numeration works, after you've studied math as advanced as algebra
and trigonometry? The reason is to better understand other numeration systems, by ¯rst knowing
the how's and why's of the one you're already used to.
The decimal numeration system uses ten ciphers, and place-weights that are multiples of ten.
What if we made a numeration system with the same strategy of weighted places, except with fewer
or more ciphers?
The binary numeration system is such a system. Instead of ten di®erent cipher symbols, with
each weight constant being ten times the one before it, we only have two cipher symbols, and each
weight constant is twice as much as the one before it. The two allowable cipher symbols for the
binary system of numeration are "1" and "0," and these ciphers are arranged right-to-left in doubling
values of weight. The rightmost place is the ones place, just as with decimal notation. Proceeding
to the left, we have the twos place, the fours place, the eights place, the sixteens place, and so on.
For example, the following binary number can be expressed, just like the decimal number 1206, as
a sum of each cipher value times its respective weight constant:
11010 = 2 + 8 + 16 = 26
11010 = (1 x 16) + (1 x 8) + (0 x 4) + (1 x 2) + (0 x 1)
This can get quite confusing, as I've written a number with binary numeration (11010), and
then shown its place values and total in standard, decimal numeration form (16 + 8 + 2 = 26). In
the above example, we're mixing two di®erent kinds of numerical notation. To avoid unnecessary
confusion, we have to denote which form of numeration we're using when we write (or type!).
Typically, this is done in subscript form, with a "2" for binary and a "10" for decimal, so the binary
number 110102 is equal to the decimal number 2610.
The subscripts are not mathematical operation symbols like superscripts (exponents) are. All
they do is indicate what system of numeration we're using when we write these symbols for other
people to read. If you see "310", all this means is the number three written using decimal numeration.
However, if you see "310", this means something completely di®erent: three to the tenth power
(59,049). As usual, if no subscript is shown, the cipher(s) are assumed to be representing a decimal
number.
Commonly, the number of cipher types (and therefore, the place-value multiplier) used in a
numeration system is called that system's base. Binary is referred to as "base two" numeration, and
decimal as "base ten." Additionally, we refer to each cipher position in binary as a bit rather than
the familiar word digit used in the decimal system.
8 CHAPTER 1. NUMERATION SYSTEMS
Now, why would anyone use binary numeration? The decimal system, with its ten ciphers, makes
a lot of sense, being that we have ten ¯ngers on which to count between our two hands. (It is inter-
esting that some ancient central American cultures used numeration systems with a base of twenty.
Presumably, they used both ¯ngers and toes to count!!). But the primary reason that the binary
numeration system is used in modern electronic computers is because of the ease of representing two
cipher states (0 and 1) electronically. With relatively simple circuitry, we can perform mathematical
operations on binary numbers by representing each bit of the numbers by a circuit which is either on
(current) or o® (no current). Just like the abacus with each rod representing another decimal digit,
we simply add more circuits to give us more bits to symbolize larger numbers. Binary numeration
also lends itself well to the storage and retrieval of numerical information: on magnetic tape (spots
of iron oxide on the tape either being magnetized for a binary "1" or demagnetized for a binary "0"),
optical disks (a laser-burned pit in the aluminum foil representing a binary "1" and an unburned
spot representing a binary "0"), or a variety of other media types.
Before we go on to learning exactly how all this is done in digital circuitry, we need to become
more familiar with binary and other associated systems of numeration.
1.3 Decimal versus binary numeration
Let's count from zero to twenty using four di®erent kinds of numeration systems: hash marks,
Roman numerals, decimal, and binary:
System: Hash Marks Roman Decimal Binary
------- ---------- ----- ------- ------
Zero n/a n/a 0 0
One j I 1 1
Two jj II 2 10
Three jjj III 3 11
Four jjjj IV 4 100
Five /jjj/ V 5 101
Six /jjj/ j VI 6 110
Seven /jjj/ jj VII 7 111
Eight /jjj/ jjj VIII 8 1000
Nine /jjj/ jjjj IX 9 1001
Ten /jjj/ /jjj/ X 10 1010
Eleven /jjj/ /jjj/ j XI 11 1011
Twelve /jjj/ /jjj/ jj XII 12 1100
Thirteen /jjj/ /jjj/ jjj XIII 13 1101
Fourteen /jjj/ /jjj/ jjjj XIV 14 1110
Fifteen /jjj/ /jjj/ /jjj/ XV 15 1111
Sixteen /jjj/ /jjj/ /jjj/ j XVI 16 10000
Seventeen /jjj/ /jjj/ /jjj/ jj XVII 17 10001
Eighteen /jjj/ /jjj/ /jjj/ jjj XVIII 18 10010
Nineteen /jjj/ /jjj/ /jjj/ jjjj XIX 19 10011
Twenty /jjj/ /jjj/ /jjj/ /jjj/ XX 20 10100
Neither hash marks nor the Roman system are very practical for symbolizing large numbers.
1.3. DECIMAL VERSUS BINARY NUMERATION 9
Obviously, place-weighted systems such as decimal and binary are more e±cient for the task. No-
tice, though, how much shorter decimal notation is over binary notation, for the same number of
quantities. What takes ¯ve bits in binary notation only takes two digits in decimal notation.
This raises an interesting question regarding di®erent numeration systems: how large of a number
can be represented with a limited number of cipher positions, or places? With the crude hash-mark
system, the number of places IS the largest number that can be represented, since one hash mark
"place" is required for every integer step. For place-weighted systems of numeration, however, the
answer is found by taking base of the numeration system (10 for decimal, 2 for binary) and raising
it to the power of the number of places. For example, 5 digits in a decimal numeration system
can represent 100,000 di®erent integer number values, from 0 to 99,999 (10 to the 5th power =
100,000). 8 bits in a binary numeration system can represent 256 di®erent integer number values,
from 0 to 11111111 (binary), or 0 to 255 (decimal), because 2 to the 8th power equals 256. With
each additional place position to the number ¯eld, the capacity for representing numbers increases
by a factor of the base (10 for decimal, 2 for binary).
An interesting footnote for this topic is the one of the ¯rst electronic digital computers, the
Eniac. The designers of the Eniac chose to represent numbers in decimal form, digitally, using a
series of circuits called "ring counters" instead of just going with the binary numeration system, in
an e®ort to minimize the number of circuits required to represent and calculate very large numbers.
This approach turned out to be counter-productive, and virtually all digital computers since then
have been purely binary in design.
To convert a number in binary numeration to its equivalent in decimal form, all you have to
do is calculate the sum of all the products of bits with their respective place-weight constants. To
illustrate:
Convert 110011012 to decimal form:
bits = 1 1 0 0 1 1 0 1
. - - - - - - - -
weight = 1 6 3 1 8 4 2 1
(in decimal 2 4 2 6
notation) 8
The bit on the far right side is called the Least Signi¯cant Bit (LSB), because it stands in the
place of the lowest weight (the one's place). The bit on the far left side is called the Most Signi¯cant
Bit (MSB), because it stands in the place of the highest weight (the one hundred twenty-eight's
place). Remember, a bit value of "1" means that the respective place weight gets added to the total
value, and a bit value of "0" means that the respective place weight does not get added to the total
value. With the above example, we have:
12810 + 6410 + 810 + 410 + 110 = 20510
If we encounter a binary number with a dot (.), called a "binary point" instead of a decimal
point, we follow the same procedure, realizing that each place weight to the right of the point is
one-half the value of the one to the left of it (just as each place weight to the right of a decimal
point is one-tenth the weight of the one to the left of it). For example:
Convert 101.0112 to decimal form:
10 CHAPTER 1. NUMERATION SYSTEMS
.
bits = 1 0 1 . 0 1 1
. - - - - - - -
weight = 4 2 1 1 1 1
(in decimal / / /
notation) 2 4 8
410 + 110 + 0.2510 + 0.12510 = 5.37510
1.4 Octal and hexadecimal numeration
Because binary numeration requires so many bits to represent relatively small numbers compared
to the economy of the decimal system, analyzing the numerical states inside of digital electronic
circuitry can be a tedious task. Computer programmers who design sequences of number codes
instructing a computer what to do would have a very di±cult task if they were forced to work with
nothing but long strings of 1's and 0's, the "native language" of any digital circuit. To make it easier
for human engineers, technicians, and programmers to "speak" this language of the digital world,
other systems of place-weighted numeration have been made which are very easy to convert to and
from binary.
One of those numeration systems is called octal, because it is a place-weighted system with a
base of eight. Valid ciphers include the symbols 0, 1, 2, 3, 4, 5, 6, and 7. Each place weight di®ers
from the one next to it by a factor of eight.
Another system is called hexadecimal, because it is a place-weighted system with a base of sixteen.
Valid ciphers include the normal decimal symbols 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9, plus six alphabetical
characters A, B, C, D, E, and F, to make a total of sixteen. As you might have guessed already,
each place weight di®ers from the one before it by a factor of sixteen.
Let's count again from zero to twenty using decimal, binary, octal, and hexadecimal to contrast
these systems of numeration:
Number Decimal Binary Octal Hexadecimal
------ ------- ------- ----- -----------
Zero 0 0 0 0
One 1 1 1 1
Two 2 10 2 2
Three 3 11 3 3
Four 4 100 4 4
Five 5 101 5 5
Six 6 110 6 6
Seven 7 111 7 7
Eight 8 1000 10 8
Nine 9 1001 11 9
Ten 10 1010 12 A
Eleven 11 1011 13 B
Twelve 12 1100 14 C
1.4. OCTAL AND HEXADECIMAL NUMERATION 11
Thirteen 13 1101 15 D
Fourteen 14 1110 16 E
Fifteen 15 1111 17 F
Sixteen 16 10000 20 10
Seventeen 17 10001 21 11
Eighteen 18 10010 22 12
Nineteen 19 10011 23 13
Twenty 20 10100 24 14
Octal and hexadecimal numeration systems would be pointless if not for their ability to be easily
converted to and from binary notation. Their primary purpose in being is to serve as a "shorthand"
method of denoting a number represented electronically in binary form. Because the bases of octal
(eight) and hexadecimal (sixteen) are even multiples of binary's base (two), binary bits can be
grouped together and directly converted to or from their respective octal or hexadecimal digits.
With octal, the binary bits are grouped in three's (because 23 = 8), and with hexadecimal, the
binary bits are grouped in four's (because 24 = 16):
BINARY TO OCTAL CONVERSION
Convert 10110111.12 to octal:
.
. implied zero implied zeros
. j jj
. 010 110 111 100
Convert each group of bits --- --- --- . ---
to its octal equivalent: 2 6 7 4
.
Answer: 10110111.12 = 267.48
We had to group the bits in three's, from the binary point left, and from the binary point right,
adding (implied) zeros as necessary to make complete 3-bit groups. Each octal digit was translated
from the 3-bit binary groups. Binary-to-Hexadecimal conversion is much the same:
BINARY TO HEXADECIMAL CONVERSION
Convert 10110111.12 to hexadecimal:
.
. implied zeros
. jjj
. 1011 0111 1000
Convert each group of bits ---- ---- . ----
to its hexadecimal equivalent: B 7 8
.
Answer: 10110111.12 = B7.816
Here we had to group the bits in four's, from the binary point left, and from the binary point
right, adding (implied) zeros as necessary to make complete 4-bit groups:
12 CHAPTER 1. NUMERATION SYSTEMS
Likewise, the conversion from either octal or hexadecimal to binary is done by taking each octal
or hexadecimal digit and converting it to its equivalent binary (3 or 4 bit) group, then putting all
the binary bit groups together.
Incidentally, hexadecimal notation is more popular, because binary bit groupings in digital equip-
ment are commonly multiples of eight (8, 16, 32, 64, and 128 bit), which are also multiples of 4.
Octal, being based on binary bit groups of 3, doesn't work out evenly with those common bit group
sizings.
1.5 Octal and hexadecimal to decimal conversion
Although the prime intent of octal and hexadecimal numeration systems is for the "shorthand"
representation of binary numbers in digital electronics, we sometimes have the need to convert from
either of those systems to decimal form. Of course, we could simply convert the hexadecimal or
octal format to binary, then convert from binary to decimal, since we already know how to do both,
but we can also convert directly.
Because octal is a base-eight numeration system, each place-weight value di®ers from either
adjacent place by a factor of eight. For example, the octal number 245.37 can be broken down into
place values as such:
octal
digits = 2 4 5 . 3 7
. - - - - - -
weight = 6 8 1 1 1
(in decimal 4 / /
notation) 8 6
. 4
The decimal value of each octal place-weight times its respective cipher multiplier can be deter-
mined as follows:
(2 x 6410) + (4 x 810) + (5 x 110) + (3 x 0.12510) +
(7 x 0.01562510) = 165.48437510
The technique for converting hexadecimal notation to decimal is the same, except that each
successive place-weight changes by a factor of sixteen. Simply denote each digit's weight, multiply
each hexadecimal digit value by its respective weight (in decimal form), then add up all the decimal
values to get a total. For example, the hexadecimal number 30F.A916 can be converted like this:
hexadecimal
digits = 3 0 F . A 9
. - - - - - -
weight = 2 1 1 1 1
(in decimal 5 6 / /
notation) 6 1 2
. 6 5
1.6. CONVERSION FROM DECIMAL NUMERATION 13
. 6
(3 x 25610) + (0 x 1610) + (15 x 110) + (10 x 0.062510) +
(9 x 0.0039062510) = 783.6601562510
These basic techniques may be used to convert a numerical notation of any base into decimal
form, if you know the value of that numeration system's base.
1.6 Conversion from decimal numeration
Because octal and hexadecimal numeration systems have bases that are multiples of binary (base 2),
conversion back and forth between either hexadecimal or octal and binary is very easy. Also, because
we are so familiar with the decimal system, converting binary, octal, or hexadecimal to decimal
form is relatively easy (simply add up the products of cipher values and place-weights). However,
conversion from decimal to any of these "strange" numeration systems is a di®erent matter.
The method which will probably make the most sense is the "trial-and-¯t" method, where you
try to "¯t" the binary, octal, or hexadecimal notation to the desired value as represented in decimal
form. For example, let's say that I wanted to represent the decimal value of 87 in binary form. Let's
start by drawing a binary number ¯eld, complete with place-weight values:
.
. - - - - - - - -
weight = 1 6 3 1 8 4 2 1
(in decimal 2 4 2 6
notation) 8
Well, we know that we won't have a "1" bit in the 128's place, because that would immediately
give us a value greater than 87. However, since the next weight to the right (64) is less than 87, we
know that we must have a "1" there.
. 1
. - - - - - - - Decimal value so far = 6410
weight = 6 3 1 8 4 2 1
(in decimal 4 2 6
notation)
If we were to make the next place to the right a "1" as well, our total value would be 6410 +
3210, or 9610. This is greater than 8710, so we know that this bit must be a "0". If we make the
next (16's) place bit equal to "1," this brings our total value to 6410 + 1610, or 8010, which is closer
to our desired value (8710) without exceeding it:
. 1 0 1
. - - - - - - - Decimal value so far = 8010
weight = 6 3 1 8 4 2 1
(in decimal 4 2 6
14 CHAPTER 1. NUMERATION SYSTEMS
notation)
By continuing in this progression, setting each lesser-weight bit as we need to come up to our
desired total value without exceeding it, we will eventually arrive at the correct ¯gure:
. 1 0 1 0 1 1 1
. - - - - - - - Decimal value so far = 8710
weight = 6 3 1 8 4 2 1
(in decimal 4 2 6
notation)
This trial-and-¯t strategy will work with octal and hexadecimal conversions, too. Let's take the
same decimal ¯gure, 8710, and convert it to octal numeration:
.
. - - -
weight = 6 8 1
(in decimal 4
notation)
If we put a cipher of "1" in the 64's place, we would have a total value of 6410 (less than 8710).
If we put a cipher of "2" in the 64's place, we would have a total value of 12810 (greater than 8710).
This tells us that our octal numeration must start with a "1" in the 64's place:
. 1
. - - - Decimal value so far = 6410
weight = 6 8 1
(in decimal 4
notation)
Now, we need to experiment with cipher values in the 8's place to try and get a total (decimal)
value as close to 87 as possible without exceeding it. Trying the ¯rst few cipher options, we get:
"1" = 6410 + 810 = 7210
"2" = 6410 + 1610 = 8010
"3" = 6410 + 2410 = 8810
A cipher value of "3" in the 8's place would put us over the desired total of 8710, so "2" it is!
. 1 2
. - - - Decimal value so far = 8010
weight = 6 8 1
(in decimal 4
notation)
Now, all we need to make a total of 87 is a cipher of "7" in the 1's place:
1.6. CONVERSION FROM DECIMAL NUMERATION 15
. 1 2 7
. - - - Decimal value so far = 8710
weight = 6 8 1
(in decimal 4
notation)
Of course, if you were paying attention during the last section on octal/binary conversions,
you will realize that we can take the binary representation of (decimal) 8710, which we previously
determined to be 10101112, and easily convert from that to octal to check our work:
. Implied zeros
. jj
. 001 010 111 Binary
. --- --- ---
. 1 2 7 Octal
.
Answer: 10101112 = 1278
Can we do decimal-to-hexadecimal conversion the same way? Sure, but who would want to?
This method is simple to understand, but laborious to carry out. There is another way to do these
conversions, which is essentially the same (mathematically), but easier to accomplish.
This other method uses repeated cycles of division (using decimal notation) to break the decimal
numeration down into multiples of binary, octal, or hexadecimal place-weight values. In the ¯rst
cycle of division, we take the original decimal number and divide it by the base of the numeration
system that we're converting to (binary=2 octal=8, hex=16). Then, we take the whole-number
portion of division result (quotient) and divide it by the base value again, and so on, until we end
up with a quotient of less than 1. The binary, octal, or hexadecimal digits are determined by the
"remainders" left over by each division step. Let's see how this works for binary, with the decimal
example of 8710:
. 87 Divide 87 by 2, to get a quotient of 43.5
. --- = 43.5 Division "remainder" = 1, or the < 1 portion
. 2 of the quotient times the divisor (0.5 x 2)
.
. 43 Take the whole-number portion of 43.5 (43)
. --- = 21.5 and divide it by 2 to get 21.5, or 21 with
. 2 a remainder of 1
.
. 21 And so on . . . remainder = 1 (0.5 x 2)
. --- = 10.5
. 2
.
. 10 And so on . . . remainder = 0
. --- = 5.0
. 2
.
16 CHAPTER 1. NUMERATION SYSTEMS
. 5 And so on . . . remainder = 1 (0.5 x 2)
. --- = 2.5
. 2
.
. 2 And so on . . . remainder = 0
. --- = 1.0
. 2
.
. 1 . . . until we get a quotient of less than 1
. --- = 0.5 remainder = 1 (0.5 x 2)
. 2
The binary bits are assembled from the remainders of the successive division steps, beginning
with the LSB and proceeding to the MSB. In this case, we arrive at a binary notation of 10101112.
When we divide by 2, we will always get a quotient ending with either ".0" or ".5", i.e. a remainder
of either 0 or 1. As was said before, this repeat-division technique for conversion will work for
numeration systems other than binary. If we were to perform successive divisions using a di®erent
number, such as 8 for conversion to octal, we will necessarily get remainders between 0 and 7. Let's
try this with the same decimal number, 8710:
. 87 Divide 87 by 8, to get a quotient of 10.875
. --- = 10.875 Division "remainder" = 7, or the < 1 portion
. 8 of the quotient times the divisor (.875 x 8)
.
. 10
. --- = 1.25 Remainder = 2
. 8
.
. 1
. --- = 0.125 Quotient is less than 1, so we'll stop here.
. 8 Remainder = 1
.
. RESULT: 8710 = 1278
We can use a similar technique for converting numeration systems dealing with quantities less
than 1, as well. For converting a decimal number less than 1 into binary, octal, or hexadecimal,
we use repeated multiplication, taking the integer portion of the product in each step as the next
digit of our converted number. Let's use the decimal number 0.812510 as an example, converting to
binary:
. 0.8125 x 2 = 1.625 Integer portion of product = 1
.
. 0.625 x 2 = 1.25 Take < 1 portion of product and remultiply
. Integer portion of product = 1
.
. 0.25 x 2 = 0.5 Integer portion of product = 0
1.6. CONVERSION FROM DECIMAL NUMERATION 17
.
. 0.5 x 2 = 1.0 Integer portion of product = 1
. Stop when product is a pure integer
. (ends with .0)
.
. RESULT: 0.812510 = 0.11012
As with the repeat-division process for integers, each step gives us the next digit (or bit) further
away from the "point." With integer (division), we worked from the LSB to the MSB (right-to-left),
but with repeated multiplication, we worked from the left to the right. To convert a decimal number
greater than 1, with a < 1 component, we must use both techniques, one at a time. Take the decimal
example of 54.4062510, converting to binary:
REPEATED DIVISION FOR THE INTEGER PORTION:
.
. 54
. --- = 27.0 Remainder = 0
. 2
.
. 27
. --- = 13.5 Remainder = 1 (0.5 x 2)
. 2
.
. 13
. --- = 6.5 Remainder = 1 (0.5 x 2)
. 2
.
. 6
. --- = 3.0 Remainder = 0
. 2
.
. 3
. --- = 1.5 Remainder = 1 (0.5 x 2)
. 2
.
. 1
. --- = 0.5 Remainder = 1 (0.5 x 2)
. 2
.
PARTIAL ANSWER: 5410 = 1101102
REPEATED MULTIPLICATION FOR THE < 1 PORTION:
.
. 0.40625 x 2 = 0.8125 Integer portion of product = 0
.
. 0.8125 x 2 = 1.625 Integer portion of product = 1
18 CHAPTER 1. NUMERATION SYSTEMS
.
. 0.625 x 2 = 1.25 Integer portion of product = 1
.
. 0.25 x 2 = 0.5 Integer portion of product = 0
.
. 0.5 x 2 = 1.0 Integer portion of product = 1
.
. PARTIAL ANSWER: 0.4062510 = 0.011012
.
. COMPLETE ANSWER: 5410 + 0.4062510 = 54.4062510
.
. 1101102 + 0.011012 = 110110.011012
Chapter 2
BINARY ARITHMETIC
Contents
2.1 Numbers versus numeration . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Binary addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Negative binary numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Over°ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Bit groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1 Numbers versus numeration
It is imperative to understand that the type of numeration system used to represent numbers has
no impact upon the outcome of any arithmetical function (addition, subtraction, multiplication,
division, roots, powers, or logarithms). A number is a number is a number; one plus one will always
equal two (so long as we're dealing with real numbers), no matter how you symbolize one, one,
and two. A prime number in decimal form is still prime if it's shown in binary form, or octal, or
hexadecimal. ¼ is still the ratio between the circumference and diameter of a circle, no matter what
symbol(s) you use to denote its value. The essential functions and interrelations of mathematics
are una®ected by the particular system of symbols we might choose to represent quantities. This
distinction between numbers and systems of numeration is critical to understand.
The essential distinction between the two is much like that between an object and the spoken
word(s) we associate with it. A house is still a house regardless of whether we call it by its English
name house or its Spanish name casa. The ¯rst is the actual thing, while the second is merely the
symbol for the thing.
That being said, performing a simple arithmetic operation such as addition (longhand) in binary
form can be confusing to a person accustomed to working with decimal numeration only. In this
lesson, we'll explore the techniques used to perform simple arithmetic functions on binary numbers,
since these techniques will be employed in the design of electronic circuits to do the same. You
might take longhand addition and subtraction for granted, having used a calculator for so long, but
19
20 CHAPTER 2. BINARY ARITHMETIC
deep inside that calculator's circuitry all those operations are performed "longhand," using binary
numeration. To understand how that's accomplished, we need to review to the basics of arithmetic.
2.2 Binary addition
Adding binary numbers is a very simple task, and very similar to the longhand addition of decimal
numbers. As with decimal numbers, you start by adding the bits (digits) one column, or place
weight, at a time, from right to left. Unlike decimal addition, there is little to memorize in the way
of rules for the addition of binary bits:
0 + 0 = 0
1 + 0 = 1
0 + 1 = 1
1 + 1 = 10
1 + 1 + 1 = 11
Just as with decimal addition, when the sum in one column is a two-bit (two-digit) number, the
least signi¯cant ¯gure is written as part of the total sum and the most signi¯cant ¯gure is "carried"
to the next left column. Consider the following examples:
. 11 1 <--- Carry bits -----> 11
. 1001101 1001001 1000111
. + 0010010 + 0011001 + 0010110
. --------- --------- ---------
. 1011111 1100010 1011101
The addition problem on the left did not require any bits to be carried, since the sum of bits in
each column was either 1 or 0, not 10 or 11. In the other two problems, there de¯nitely were bits to
be carried, but the process of addition is still quite simple.
As we'll see later, there are ways that electronic circuits can be built to perform this very task of
addition, by representing each bit of each binary number as a voltage signal (either "high," for a 1;
or "low" for a 0). This is the very foundation of all the arithmetic which modern digital computers
perform.
2.3 Negative binary numbers
With addition being easily accomplished, we can perform the operation of subtraction with the same
technique simply by making one of the numbers negative. For example, the subtraction problem
of 7 - 5 is essentially the same as the addition problem 7 + (-5). Since we already know how to
represent positive numbers in binary, all we need to know now is how to represent their negative
counterparts and we'll be able to subtract.
Usually we represent a negative decimal number by placing a minus sign directly to the left of
the most signi¯cant digit, just as in the example above, with -5. However, the whole purpose of
using binary notation is for constructing on/o® circuits that can represent bit values in terms of
voltage (2 alternative values: either "high" or "low"). In this context, we don't have the luxury of a
2.3. NEGATIVE BINARY NUMBERS 21
third symbol such as a "minus" sign, since these circuits can only be on or o® (two possible states).
One solution is to reserve a bit (circuit) that does nothing but represent the mathematical sign:
. 1012 = 510 (positive)
.
. Extra bit, representing sign (0=positive, 1=negative)
. j
. 01012 = 510 (positive)
.
. Extra bit, representing sign (0=positive, 1=negative)
. j
. 11012 = -510 (negative)
As you can see, we have to be careful when we start using bits for any purpose other than
standard place-weighted values. Otherwise, 11012 could be misinterpreted as the number thirteen
when in fact we mean to represent negative ¯ve. To keep things straight here, we must ¯rst decide
how many bits are going to be needed to represent the largest numbers we'll be dealing with, and
then be sure not to exceed that bit ¯eld length in our arithmetic operations. For the above example,
I've limited myself to the representation of numbers from negative seven (11112) to positive seven
(01112), and no more, by making the fourth bit the "sign" bit. Only by ¯rst establishing these limits
can I avoid confusion of a negative number with a larger, positive number.
Representing negative ¯ve as 11012 is an example of the sign-magnitude system of negative
binary numeration. By using the leftmost bit as a sign indicator and not a place-weighted value, I
am sacri¯cing the "pure" form of binary notation for something that gives me a practical advantage:
the representation of negative numbers. The leftmost bit is read as the sign, either positive or
negative, and the remaining bits are interpreted according to the standard binary notation: left to
right, place weights in multiples of two.
As simple as the sign-magnitude approach is, it is not very practical for arithmetic purposes. For
instance, how do I add a negative ¯ve (11012) to any other number, using the standard technique
for binary addition? I'd have to invent a new way of doing addition in order for it to work, and
if I do that, I might as well just do the job with longhand subtraction; there's no arithmetical
advantage to using negative numbers to perform subtraction through addition if we have to do it
with sign-magnitude numeration, and that was our goal!
There's another method for representing negative numbers which works with our familiar tech-
nique of longhand addition, and also happens to make more sense from a place-weighted numeration
point of view, called complementation. With this strategy, we assign the leftmost bit to serve a
special purpose, just as we did with the sign-magnitude approach, de¯ning our number limits just
as before. However, this time, the leftmost bit is more than just a sign bit; rather, it possesses a
negative place-weight value. For example, a value of negative ¯ve would be represented as such:
Extra bit, place weight = negative eight
. j
. 10112 = 510 (negative)
.
. (1 x -810) + (0 x 410) + (1 x 210) + (1 x 110) = -510
22 CHAPTER 2. BINARY ARITHMETIC
With the right three bits being able to represent a magnitude from zero through seven, and
the leftmost bit representing either zero or negative eight, we can successfully represent any integer
number from negative seven (10012 = -810 + 110 = -110) to positive seven (01112 = 010 + 710 =
710).
Representing positive numbers in this scheme (with the fourth bit designated as the negative
weight) is no di®erent from that of ordinary binary notation. However, representing negative num-
bers is not quite as straightforward:
zero 0000
positive one 0001 negative one 1111
positive two 0010 negative two 1110
positive three 0011 negative three 1101
positive four 0100 negative four 1100
positive five 0101 negative five 1011
positive six 0110 negative six 1010
positive seven 0111 negative seven 1001
. negative eight 1000
Note that the negative binary numbers in the right column, being the sum of the right three
bits' total plus the negative eight of the leftmost bit, don't "count" in the same progression as the
positive binary numbers in the left column. Rather, the right three bits have to be set at the proper
value to equal the desired (negative) total when summed with the negative eight place value of the
leftmost bit.
Those right three bits are referred to as the two's complement of the corresponding positive
number. Consider the following comparison:
positive number two's complement
--------------- ----------------
001 111
010 110
011 101
100 100
101 011
110 010
111 001
In this case, with the negative weight bit being the fourth bit (place value of negative eight), the
two's complement for any positive number will be whatever value is needed to add to negative eight
to make that positive value's negative equivalent. Thankfully, there's an easy way to ¯gure out the
two's complement for any binary number: simply invert all the bits of that number, changing all
1's to 0's and vice versa (to arrive at what is called the one's complement) and then add one! For
example, to obtain the two's complement of ¯ve (1012), we would ¯rst invert all the bits to obtain
0102 (the "one's complement"), then add one to obtain 0112, or -510 in three-bit, two's complement
form.
Interestingly enough, generating the two's complement of a binary number works the same if you
manipulate all the bits, including the leftmost (sign) bit at the same time as the magnitude bits.
2.4. SUBTRACTION 23
Let's try this with the former example, converting a positive ¯ve to a negative ¯ve, but performing
the complementation process on all four bits. We must be sure to include the 0 (positive) sign bit
on the original number, ¯ve (01012). First, inverting all bits to obtain the one's complement: 10102.
Then, adding one, we obtain the ¯nal answer: 10112, or -510 expressed in four-bit, two's complement
form.
It is critically important to remember that the place of the negative-weight bit must be already
determined before any two's complement conversions can be done. If our binary numeration ¯eld
were such that the eighth bit was designated as the negative-weight bit (100000002), we'd have to
determine the two's complement based on all seven of the other bits. Here, the two's complement of
¯ve (00001012) would be 11110112. A positive ¯ve in this system would be represented as 000001012,
and a negative ¯ve as 111110112.
2.4 Subtraction
We can subtract one binary number from another by using the standard techniques adapted for
decimal numbers (subtraction of each bit pair, right to left, "borrowing" as needed from bits to
the left). However, if we can leverage the already familiar (and easier) technique of binary addition
to subtract, that would be better. As we just learned, we can represent negative binary numbers
by using the "two's complement" method and a negative place-weight bit. Here, we'll use those
negative binary numbers to subtract through addition. Here's a sample problem:
Subtraction: 710 - 510 Addition equivalent: 710 + (-510)
If all we need to do is represent seven and negative ¯ve in binary (two's complemented) form, all
we need is three bits plus the negative-weight bit:
positive seven = 01112
negative five = 10112
Now, let's add them together:
. 1111 <--- Carry bits
. 0111
. + 1011
. ------
. 10010
. j
. Discard extra bit
.
. Answer = 00102
Since we've already de¯ned our number bit ¯eld as three bits plus the negative-weight bit, the
¯fth bit in the answer (1) will be discarded to give us a result of 00102, or positive two, which is the
correct answer.
Another way to understand why we discard that extra bit is to remember that the leftmost bit
of the lower number possesses a negative weight, in this case equal to negative eight. When we add
24 CHAPTER 2. BINARY ARITHMETIC
these two binary numbers together, what we're actually doing with the MSBs is subtracting the
lower number's MSB from the upper number's MSB. In subtraction, one never "carries" a digit or
bit on to the next left place-weight.
Let's try another example, this time with larger numbers. If we want to add -2510 to 1810,
we must ¯rst decide how large our binary bit ¯eld must be. To represent the largest (absolute
value) number in our problem, which is twenty-¯ve, we need at least ¯ve bits, plus a sixth bit
for the negative-weight bit. Let's start by representing positive twenty-¯ve, then ¯nding the two's
complement and putting it all together into one numeration:
+2510 = 0110012 (showing all six bits)
One's complement of 110012 = 1001102
One's complement + 1 = two's complement = 1001112
-2510 = 1001112
Essentially, we're representing negative twenty-¯ve by using the negative-weight (sixth) bit with
a value of negative thirty-two, plus positive seven (binary 1112).
Now, let's represent positive eighteen in binary form, showing all six bits:
. 1810 = 0100102
.
. Now, let's add them together and see what we get:
.
. 11 <--- Carry bits
. 100111
. + 010010
. --------
. 111001
Since there were no "extra" bits on the left, there are no bits to discard. The leftmost bit on
the answer is a 1, which means that the answer is negative, in two's complement form, as it should
be. Converting the answer to decimal form by summing all the bits times their respective weight
values, we get:
(1 x -3210) + (1 x 1610) + (1 x 810) + (1 x 110) = -710
Indeed -710 is the proper sum of -2510 and 1810.
2.5 Over°ow
One caveat with signed binary numbers is that of over°ow, where the answer to an addition or
subtraction problem exceeds the magnitude which can be represented with the alloted number of
bits. Remember that the place of the sign bit is ¯xed from the beginning of the problem. With the
last example problem, we used ¯ve binary bits to represent the magnitude of the number, and the
left-most (sixth) bit as the negative-weight, or sign, bit. With ¯ve bits to represent magnitude, we
have a representation range of 25, or thirty-two integer steps from 0 to maximum. This means that
2.5. OVERFLOW 25
we can represent a number as high as +3110 (0111112), or as low as -3210 (1000002). If we set up an
addition problem with two binary numbers, the sixth bit used for sign, and the result either exceeds
+3110 or is less than -3210, our answer will be incorrect. Let's try adding 1710 and 1910 to see how
this over°ow condition works for excessive positive numbers:
. 1710 = 100012 1910 = 100112
.
. 1 11 <--- Carry bits
. (Showing sign bits) 010001
. + 010011
. --------
. 100100
The answer (1001002), interpreted with the sixth bit as the -3210 place, is actually equal to -2810,
not +3610 as we should get with +1710 and +1910 added together! Obviously, this is not correct.
What went wrong? The answer lies in the restrictions of the six-bit number ¯eld within which we're
working Since the magnitude of the true and proper sum (3610) exceeds the allowable limit for our
designated bit ¯eld, we have an over°ow error. Simply put, six places doesn't give enough bits to
represent the correct sum, so whatever ¯gure we obtain using the strategy of discarding the left-most
"carry" bit will be incorrect.
A similar error will occur if we add two negative numbers together to produce a sum that is too
low for our six-bit binary ¯eld. Let's try adding -1710 and -1910 together to see how this works (or
doesn't work, as the case may be!):
. -1710 = 1011112 -1910 = 1011012
.
. 1 1111 <--- Carry bits
. (Showing sign bits) 101111
. + 101101
. --------
. 1011100
. j
. Discard extra bit
.
FINAL ANSWER: 0111002 = +2810
The (incorrect) answer is a positive twenty-eight. The fact that the real sum of negative seventeen
and negative nineteen was too low to be properly represented with a ¯ve bit magnitude ¯eld and a
sixth sign bit is the root cause of this di±culty.
Let's try these two problems again, except this time using the seventh bit for a sign bit, and
allowing the use of 6 bits for representing the magnitude:
. 1710 + 1910 (-1710) + (-1910)
.
. 1 11 11 1111
. 0010001 1101111
26 CHAPTER 2. BINARY ARITHMETIC
. + 0010011 + 1101101
. --------- ---------
. 01001002 110111002
. j
. Discard extra bit
.
. ANSWERS: 01001002 = +3610
. 10111002 = -3610
By using bit ¯elds su±ciently large to handle the magnitude of the sums, we arrive at the correct
answers.
In these sample problems we've been able to detect over°ow errors by performing the addition
problems in decimal form and comparing the results with the binary answers. For example, when
adding +1710 and +1910 together, we knew that the answer was supposed to be +3610, so when the
binary sum checked out to be -2810, we knew that something had to be wrong. Although this is a
valid way of detecting over°ow, it is not very e±cient. After all, the whole idea of complementation
is to be able to reliably add binary numbers together and not have to double-check the result by
adding the same numbers together in decimal form! This is especially true for the purpose of building
electronic circuits to add binary quantities together: the circuit has to be able to check itself for
over°ow without the supervision of a human being who already knows what the correct answer is.
What we need is a simple error-detection method that doesn't require any additional arithmetic.
Perhaps the most elegant solution is to check for the sign of the sum and compare it against the
signs of the numbers added. Obviously, two positive numbers added together should give a positive
result, and two negative numbers added together should give a negative result. Notice that whenever
we had a condition of over°ow in the example problems, the sign of the sum was always opposite
of the two added numbers: +1710 plus +1910 giving -2810, or -1710 plus -1910 giving +2810. By
checking the signs alone we are able to tell that something is wrong.
But what about cases where a positive number is added to a negative number? What sign should
the sum be in order to be correct. Or, more precisely, what sign of sum would necessarily indicate an
over°ow error? The answer to this is equally elegant: there will never be an over°ow error when two
numbers of opposite signs are added together! The reason for this is apparent when the nature of
over°ow is considered. Over°ow occurs when the magnitude of a number exceeds the range allowed
by the size of the bit ¯eld. The sum of two identically-signed numbers may very well exceed the
range of the bit ¯eld of those two numbers, and so in this case over°ow is a possibility. However, if a
positive number is added to a negative number, the sum will always be closer to zero than either of
the two added numbers: its magnitude must be less than the magnitude of either original number,
and so over°ow is impossible.
Fortunately, this technique of over°ow detection is easily implemented in electronic circuitry, and
it is a standard feature in digital adder circuits: a subject for a later chapter.
2.6 Bit groupings
The singular reason for learning and using the binary numeration system in electronics is to under-
stand how to design, build, and troubleshoot circuits that represent and process numerical quantities
in digital form. Since the bivalent (two-valued) system of binary bit numeration lends itself so easily
2.6. BIT GROUPINGS 27
to representation by "on" and "o®" transistor states (saturation and cuto®, respectively), it makes
sense to design and build circuits leveraging this principle to perform binary calculations.
If we were to build a circuit to represent a binary number, we would have to allocate enough
transistor circuits to represent as many bits as we desire. In other words, in designing a digital
circuit, we must ¯rst decide how many bits (maximum) we would like to be able to represent, since
each bit requires one on/o® circuit to represent it. This is analogous to designing an abacus to
digitally represent decimal numbers: we must decide how many digits we wish to handle in this
primitive "calculator" device, for each digit requires a separate rod with its own beads.
A 10-rod abacus
Each rod represents
a single decimal digit
A ten-rod abacus would be able to represent a ten-digit decimal number, or a maxmium value
of 9,999,999,999. If we wished to represent a larger number on this abacus, we would be unable to,
unless additional rods could be added to it.
In digital, electronic computer design, it is common to design the system for a common "bit
width:" a maximum number of bits allocated to represent numerical quantities. Early digital com-
puters handled bits in groups of four or eight. More modern systems handle numbers in clusters of
32 bits or more. To more conveniently express the "bit width" of such clusters in a digital computer,
speci¯c labels were applied to the more common groupings.
Eight bits, grouped together to form a single binary quantity, is known as a byte. Four bits,
grouped together as one binary number, is known by the humorous title of nibble, often spelled as
nybble.
A multitude of terms have followed byte and nibble for labeling spec¯ic groupings of binary
bits. Most of the terms shown here are informal, and have not been made "authoritative" by any
standards group or other sanctioning body. However, their inclusion into this chapter is warranted
by their occasional appearance in technical literature, as well as the levity they add to an otherwise
dry subject:
² Bit: A single, bivalent unit of binary notation. Equivalent to a decimal "digit."
² Crumb, Tydbit, or Tayste: Two bits.
² Nibble, or Nybble: Four bits.
28 CHAPTER 2. BINARY ARITHMETIC
² Nickle: Five bits.
² Byte: Eight bits.
² Deckle: Ten bits.
² Playte: Sixteen bits.
² Dynner: Thirty-two bits.
² Word: (system dependent).
The most ambiguous term by far is word, referring to the standard bit-grouping within a partic-
ular digital system. For a computer system using a 32 bit-wide "data path," a "word" would mean
32 bits. If the system used 16 bits as the standard grouping for binary quantities, a "word" would
mean 16 bits. The terms playte and dynner, by contrast, always refer to 16 and 32 bits, respectively,
regardless of the system context in which they are used.
Context dependence is likewise true for derivative terms of word, such as double word and long-
word (both meaning twice the standard bit-width), half-word (half the standard bit-width), and
quad (meaning four times the standard bit-width). One humorous addition to this somewhat boring
collection of word-derivatives is the term chawmp, which means the same as half-word. For example,
a chawmp would be 16 bits in the context of a 32-bit digital system, and 18 bits in the context of a
36-bit system. Also, the term gawble is sometimes synonymous with word.
De¯nitions for bit grouping terms were taken from Eric S. Raymond's "Jargon Lexicon," an
indexed collection of terms { both common and obscure { germane to the world of computer pro-
gramming.
Chapter 3
LOGIC GATES
Contents
3.1 Digital signals and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 The NOT gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 The "bu®er" gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Multiple-input gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.4.1 The AND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.2 The NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.3 The OR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.4 The NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.4.5 The Negative-AND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.6 The Negative-OR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.7 The Exclusive-OR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.4.8 The Exclusive-NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.5 TTL NAND and AND gates . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6 TTL NOR and OR gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.7 CMOS gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.8 Special-output gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.9 Gate universality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.9.1 Constructing the NOT function . . . . . . . . . . . . . . . . . . . . . . . . 84
3.9.2 Constructing the "bu®er" function . . . . . . . . . . . . . . . . . . . . . . 85
3.9.3 Constructing the AND function . . . . . . . . . . . . . . . . . . . . . . . . 85
3.9.4 Constructing the NAND function . . . . . . . . . . . . . . . . . . . . . . . 86
3.9.5 Constructing the OR function . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.9.6 Constructing the NOR function . . . . . . . . . . . . . . . . . . . . . . . . 88
3.10 Logic signal voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.11 DIP gate packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.12 Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
29
30 CHAPTER 3. LOGIC GATES
3.1 Digital signals and gates
While the binary numeration system is an interesting mathematical abstraction, we haven't yet seen
its practical application to electronics. This chapter is devoted to just that: practically applying the
concept of binary bits to circuits. What makes binary numeration so important to the application of
digital electronics is the ease in which bits may be represented in physical terms. Because a binary
bit can only have one of two di®erent values, either 0 or 1, any physical medium capable of switching
between two saturated states may be used to represent a bit. Consequently, any physical system
capable of representing binary bits is able to represent numerical quantities, and potentially has the
ability to manipulate those numbers. This is the basic concept underlying digital computing.
Electronic circuits are physical systems that lend themselves well to the representation of binary
numbers. Transistors, when operated at their bias limits, may be in one of two di®erent states:
either cuto® (no controlled current) or saturation (maximum controlled current). If a transistor
circuit is designed to maximize the probability of falling into either one of these states (and not
operating in the linear, or active, mode), it can serve as a physical representation of a binary bit. A
voltage signal measured at the output of such a circuit may also serve as a representation of a single
bit, a low voltage representing a binary "0" and a (relatively) high voltage representing a binary
"1." Note the following transistor circuit:
5 V
Vin = 5 V
Vout » 0 V
0 V = "low" logic level (0)
"high" input
5 V = "high" logic level (1)
"low" output
Transistor in saturation
In this circuit, the transistor is in a state of saturation by virtue of the applied input voltage
(5 volts) through the two-position switch. Because it's saturated, the transistor drops very little
voltage between collector and emitter, resulting in an output voltage of (practically) 0 volts. If
we were using this circuit to represent binary bits, we would say that the input signal is a binary
"1" and that the output signal is a binary "0." Any voltage close to full supply voltage (measured
in reference to ground, of course) is considered a "1" and a lack of voltage is considered a "0."
Alternative terms for these voltage levels are high (same as a binary "1") and low (same as a binary
"0"). A general term for the representation of a binary bit by a circuit voltage is logic level.
Moving the switch to the other position, we apply a binary "0" to the input and receive a binary
"1" at the output:
3.1. DIGITAL SIGNALS AND GATES 31
5 V
0 V = "low" logic level (0)
Vin = 0 V
Vout = 5 V
"low" input "high" output
5 V = "high" logic level (1)
Transistor in cutoff
What we've created here with a single transistor is a circuit generally known as a logic gate, or
simply gate. A gate is a special type of ampli¯er circuit designed to accept and generate voltage
signals corresponding to binary 1's and 0's. As such, gates are not intended to be used for amplifying
analog signals (voltage signals between 0 and full voltage). Used together, multiple gates may be
applied to the task of binary number storage (memory circuits) or manipulation (computing circuits),
each gate's output representing one bit of a multi-bit binary number. Just how this is done is a
subject for a later chapter. Right now it is important to focus on the operation of individual gates.
The gate shown here with the single transistor is known as an inverter, or NOT gate, because it
outputs the exact opposite digital signal as what is input. For convenience, gate circuits are generally
represented by their own symbols rather than by their constituent transistors and resistors. The
following is the symbol for an inverter:
Inverter, or NOT gate
Input Output
An alternative symbol for an inverter is shown here:
Input Output
Notice the triangular shape of the gate symbol, much like that of an operational ampli¯er. As was
stated before, gate circuits actually are ampli¯ers. The small circle, or "bubble" shown on either the
input or output terminal is standard for representing the inversion function. As you might suspect,
if we were to remove the bubble from the gate symbol, leaving only a triangle, the resulting symbol
would no longer indicate inversion, but merely direct ampli¯cation. Such a symbol and such a gate
actually do exist, and it is called a bu®er, the subject of the next section.
Like an operational ampli¯er symbol, input and output connections are shown as single wires,
the implied reference point for each voltage signal being "ground." In digital gate circuits, ground
32 CHAPTER 3. LOGIC GATES
is almost always the negative connection of a single voltage source (power supply). Dual, or "split,"
power supplies are seldom used in gate circuitry. Because gate circuits are ampli¯ers, they require
a source of power to operate. Like operational ampli¯ers, the power supply connections for digital
gates are often omitted from the symbol for simplicity's sake. If we were to show all the necessary
connections needed for operating this gate, the schematic would look something like this:
5 V
Vin Vout
Vcc
Ground
Power supply conductors are rarely shown in gate circuit schematics, even if the power supply
connections at each gate are. Minimizing lines in our schematic, we get this:
Vcc Vcc
"Vcc" stands for the constant voltage supplied to the collector of a bipolar junction transistor
circuit, in reference to ground. Those points in a gate circuit marked by the label "Vcc" are all
connected to the same point, and that point is the positive terminal of a DC voltage source, usually
5 volts.
As we will see in other sections of this chapter, there are quite a few di®erent types of logic gates,
most of which have multiple input terminals for accepting more than one signal. The output of any
gate is dependent on the state of its input(s) and its logical function.
One common way to express the particular function of a gate circuit is called a truth table. Truth
tables show all combinations of input conditions in terms of logic level states (either "high" or "low,"
"1" or "0," for each input terminal of the gate), along with the corresponding output logic level,
either "high" or "low." For the inverter, or NOT, circuit just illustrated, the truth table is very
simple indeed:
3.2. THE NOT GATE 33
Input Output
0 1
1 0
NOT gate truth table
Input Output
Truth tables for more complex gates are, of course, larger than the one shown for the NOT gate.
A gate's truth table must have as many rows as there are possibilities for unique input combinations.
For a single-input gate like the NOT gate, there are only two possibilities, 0 and 1. For a two input
gate, there are four possibilities (00, 01, 10, and 11), and thus four rows to the corresponding truth
table. For a three-input gate, there are eight possibilities (000, 001, 010, 011, 100, 101, 110, and
111), and thus a truth table with eight rows are needed. The mathematically inclined will realize
that the number of truth table rows needed for a gate is equal to 2 raised to the power of the number
of input terminals.
² REVIEW:
² In digital circuits, binary bit values of 0 and 1 are represented by voltage signals measured in
reference to a common circuit point called ground. An absence of voltage represents a binary
"0" and the presence of full DC supply voltage represents a binary "1."
² A logic gate, or simply gate, is a special form of ampli¯er circuit designed to input and output
logic level voltages (voltages intended to represent binary bits). Gate circuits are most com-
monly represented in a schematic by their own unique symbols rather than by their constituent
transistors and resistors.
² Just as with operational ampli¯ers, the power supply connections to gates are often omitted
in schematic diagrams for the sake of simplicity.
² A truth table is a standard way of representing the input/output relationships of a gate circuit,
listing all the possible input logic level combinations with their respective output logic levels.
3.2 The NOT gate
The single-transistor inverter circuit illustrated earlier is actually too crude to be of practical use
as a gate. Real inverter circuits contain more than one transistor to maximize voltage gain (so
as to ensure that the ¯nal output transistor is either in full cuto® or full saturation), and other
components designed to reduce the chance of accidental damage.
Shown here is a schematic diagram for a real inverter circuit, complete with all necessary com-
ponents for e±cient and reliable operation:
34 CHAPTER 3. LOGIC GATES
Output
Input
Vcc
Practical inverter (NOT) circuit
Q1 Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
This circuit is composed exclusively of resistors and bipolar transistors. Bear in mind that other
circuit designs are capable of performing the NOT gate function, including designs substituting
¯eld-e®ect transistors for bipolar (discussed later in this chapter).
Let's analyze this circuit for the condition where the input is "high," or in a binary "1" state.
We can simulate this by showing the input terminal connected to Vcc through a switch:
Output
Input
Vcc
Q1 Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
+
-
5 V
0 V
In this case, diode D1 will be reverse-biased, and therefore not conduct any current. In fact, the
3.2. THE NOT GATE 35
only purpose for having D1 in the circuit is to prevent transistor damage in the case of a negative
voltage being impressed on the input (a voltage that is negative, rather than positive, with respect
to ground). With no voltage between the base and emitter of transistor Q1, we would expect no
current through it, either. However, as strange as it may seem, transistor Q1 is not being used as
is customary for a transistor. In reality, Q1 is being used in this circuit as nothing more than a
back-to-back pair of diodes. The following schematic shows the real function of Q1:
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
+
-
5 V
0 V
"Q1"
The purpose of these diodes is to "steer" current to or away from the base of transistor Q2, de-
pending on the logic level of the input. Exactly how these two diodes are able to "steer" current isn't
exactly obvious at ¯rst inspection, so a short example may be necessary for understanding. Suppose
we had the following diode/resistor circuit, representing the base-emitter junctions of transistors Q2
and Q4 as single diodes, stripping away all other portions of the circuit so that we can concentrate
on the current "steered" through the two back-to-back diodes:
36 CHAPTER 3. LOGIC GATES
Vcc
R3
"Q1"
Q2(B-E)
Q4(B-E)
5 V
R1
With the input switch in the "up" position (connected to Vcc), it should be obvious that there
will be no current through the left steering diode of Q1, because there isn't any voltage in the switch-
diode-R1-switch loop to motivate electrons to °ow. However, there will be current through the right
steering diode of Q1, as well as through Q2's base-emitter diode junction and Q4's base-emitter
diode junction:
Vcc
R3
"Q1"
Q2(B-E)
Q4(B-E)
5 V
R1
This tells us that in the real gate circuit, transistors Q2 and Q4 will have base current, which
will turn them on to conduct collector current. The total voltage dropped between the base of Q1
(the node joining the two back-to-back steering diodes) and ground will be about 2.1 volts, equal to
the combined voltage drops of three PN junctions: the right steering diode, Q2's base-emitter diode,
and Q4's base-emitter diode.
Now, let's move the input switch to the "down" position and see what happens:
3.2. THE NOT GATE 37
Vcc
R3
"Q1"
Q2(B-E)
Q4(B-E)
5 V
R1
If we were to measure current in this circuit, we would ¯nd that all of the current goes through
the left steering diode of Q1 and none of it through the right diode. Why is this? It still appears as
though there is a complete path for current through Q4's diode, Q2's diode, the right diode of the
pair, and R1, so why will there be no current through that path?
Remember that PN junction diodes are very nonlinear devices: they do not even begin to conduct
current until the forward voltage applied across them reaches a certain minimum quantity, approx-
imately 0.7 volts for silicon and 0.3 volts for germanium. And then when they begin to conduct
current, they will not drop substantially more than 0.7 volts. When the switch in this circuit is in
the "down" position, the left diode of the steering diode pair is fully conducting, and so it drops
about 0.7 volts across it and no more.
Vcc
R3
"Q1"
Q2(B-E)
Q4(B-E)
5 V
R1
0.7 V
+
-
Recall that with the switch in the "up" position (transistors Q2 and Q4 conducting), there was
about 2.1 volts dropped between those same two points (Q1's base and ground), which also happens
to be the minimum voltage necessary to forward-bias three series-connected silicon PN junctions
into a state of conduction. The 0.7 volts provided by the left diode's forward voltage drop is simply
insu±cient to allow any electron °ow through the series string of the right diode, Q2's diode, and
the R3//Q4 diode parallel subcircuit, and so no electrons °ow through that path. With no current
38 CHAPTER 3. LOGIC GATES
through the bases of either transistor Q2 or Q4, neither one will be able to conduct collector current:
transistors Q2 and Q4 will both be in a state of cuto®.
Consequently, this circuit con¯guration allows 100 percent switching of Q2 base current (and
therefore control over the rest of the gate circuit, including voltage at the output) by diversion of
current through the left steering diode.
In the case of our example gate circuit, the input is held "high" by the switch (connected to Vcc),
making the left steering diode (zero voltage dropped across it). However, the right steering diode is
conducting current through the base of Q2, through resistor R1:
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
+
-
5 V
0 V
"Q1"
With base current provided, transistor Q2 will be turned "on." More speci¯cally, it will be
saturated by virtue of the more-than-adequate current allowed by R1 through the base. With Q2
saturated, resistor R3 will be dropping enough voltage to forward-bias the base-emitter junction of
transistor Q4, thus saturating it as well:
3.2. THE NOT GATE 39
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
+
-
5 V
0 V
"Q1"
» 0 V
» 0.7 V
With Q4 saturated, the output terminal will be almost directly shorted to ground, leaving the
output terminal at a voltage (in reference to ground) of almost 0 volts, or a binary "0" ("low") logic
level. Due to the presence of diode D2, there will not be enough voltage between the base of Q3 and
its emitter to turn it on, so it remains in cuto®.
Let's see now what happens if we reverse the input's logic level to a binary "0" by actuating the
input switch:
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
"Q1"
5 V
0 V
+
-
» 5 V
40 CHAPTER 3. LOGIC GATES
Now there will be current through the left steering diode of Q1 and no current through the right
steering diode. This eliminates current through the base of Q2, thus turning it o®. With Q2 o®,
there is no longer a path for Q4 base current, so Q4 goes into cuto® as well. Q3, on the other hand,
now has su±cient voltage dropped between its base and ground to forward-bias its base-emitter
junction and saturate it, thus raising the output terminal voltage to a "high" state. In actuality,
the output voltage will be somewhere around 4 volts depending on the degree of saturation and any
load current, but still high enough to be considered a "high" (1) logic level.
With this, our simulation of the inverter circuit is complete: a "1" in gives a "0" out, and vice
versa.
The astute observer will note that this inverter circuit's input will assume a "high" state of left
°oating (not connected to either Vcc or ground). With the input terminal left unconnected, there
will be no current through the left steering diode of Q1, leaving all of R1's current to go through
Q2's base, thus saturating Q2 and driving the circuit output to a "low" state:
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc = 5 volts
+
-
5 V
0 V
"Q1"
» 0 V
» 0.7 V
(floating)
The tendency for such a circuit to assume a high input state if left °oating is one shared by
all gate circuits based on this type of design, known as Transistor-to-Transistor Logic, or TTL.
This characteristic may be taken advantage of in simplifying the design of a gate's output circuitry,
knowing that the outputs of gates typically drive the inputs of other gates. If the input of a TTL
gate circuit assumes a high state when °oating, then the output of any gate driving a TTL input
need only provide a path to ground for a low state and be °oating for a high state. This concept
may require further elaboration for full understanding, so I will explore it in detail here.
A gate circuit as we have just analyzed has the ability to handle output current in two directions:
in and out. Technically, this is known as sourcing and sinking current, respectively. When the gate
output is high, there is continuity from the output terminal to Vcc through the top output transistor
(Q3), allowing electrons to °ow from ground, through a load, into the gate's output terminal, through
the emitter of Q3, and eventually up to the Vcc power terminal (positive side of the DC power supply):
3.2. THE NOT GATE 41
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
"Q1"
5 V
0 V
+
-
» 5 V Load
Inverter gate sourcing current
To simplify this concept, we may show the output of a gate circuit as being a double-throw switch,
capable of connecting the output terminal either to Vcc or ground, depending on its state. For a
gate outputting a "high" logic level, the combination of Q3 saturated and Q4 cuto® is analogous to
a double-throw switch in the "Vcc" position, providing a path for current through a grounded load:
Input Output
Vcc
...
Load
Simplified gate circuit sourcing current
Please note that this two-position switch shown inside the gate symbol is representative of tran-
sistors Q3 and Q4 alternately connecting the output terminal to Vcc or ground, not of the switch
previously shown sending an input signal to the gate!
Conversely, when a gate circuit is outputting a "low" logic level to a load, it is analogous to
the double-throw switch being set in the "ground" position. Current will then be going the other
way if the load resistance connects to Vcc: from ground, through the emitter of Q4, out the output
terminal, through the load resistance, and back to Vcc. In this condition, the gate is said to be
sinking current:
42 CHAPTER 3. LOGIC GATES
Output
Input
Vcc
Q2
Q3
Q4
D1
D2
R1 R2
R3
R4
Vcc
Vcc = 5 volts
+
-
5 V
0 V
"Q1"
» 0.7 V
Vcc
Inverter gate sinking current
Load
Input
Output
Vcc
...
Load
Simplified gate circuit sinking current
Vcc
The combination of Q3 and Q4 working as a "push-pull" transistor pair (otherwise known as a
totem pole output) has the ability to either source current (draw in current to Vcc) or sink current
(output current from ground) to a load. However, a standard TTL gate input never needs current to
be sourced, only sunk. That is, since a TTL gate input naturally assumes a high state if left °oating,
any gate output driving a TTL input need only sink current to provide a "0" or "low" input, and
need not source current to provide a "1" or a "high" logic level at the input of the receiving gate:
3.2. THE NOT GATE 43
Input
Vcc
... ... TTL
gate
A direct connection to Vcc is not
necessary to drive the TTL gate
input high!
Input
Vcc
... ... TTL
gate
An output that "floats" when high
is sufficient.
Input
Vcc
... ... TTL
gate
Vcc
Any gate driving a TTL
input must sink some
current in the low state.
This means we have the option of simplifying the output stage of a gate circuit so as to eliminate
Q3 altogether. The result is known as an open-collector output:
44 CHAPTER 3. LOGIC GATES
Output
Input
Vcc
D1
R1 R2
R3
Inverter circuit with open-collector output
To designate open-collector output circuitry within a standard gate symbol, a special marker is
used. Shown here is the symbol for an inverter gate with open-collector output:
Inverter with opencollector
output
Please keep in mind that the "high" default condition of a °oating gate input is only true for
TTL circuitry, and not necessarily for other types, especially for logic gates constructed of ¯eld-e®ect
transistors.
² REVIEW:
² An inverter, or NOT, gate is one that outputs the opposite state as what is input. That is, a
"low" input (0) gives a "high" output (1), and vice versa.
² Gate circuits constructed of resistors and bipolar transistors as illustrated in this section are
called TTL. TTL is an acronym standing for Transistor-to-Transistor Logic. There are other
design methodologies used in gate circuits, some which use ¯eld-e®ect transistors rather than
bipolar transistors.
² A gate is said to be sourcing current when it provides a path for current between the output
terminal and the positive side of the DC power supply (Vcc). In other words, it is connecting
the output terminal to the power source (+V).
² A gate is said to be sinking current when it provides a path for current between the output
terminal and ground. In other words, it is grounding (sinking) the output terminal.
3.3. THE "BUFFER" GATE 45
² Gate circuits with totem pole output stages are able to both source and sink current. Gate
circuits with open-collector output stages are only able to sink current, and not source current.
Open-collector gates are practical when used to drive TTL gate inputs because TTL inputs
don't require current sourcing.
3.3 The "bu®er" gate
If we were to connect two inverter gates together so that the output of one fed into the input
of another, the two inversion functions would "cancel" each other out so that there would be no
inversion from input to ¯nal output:
0
1
0
0 inverted into a 1
Logic state re-inverted
to original status
Double inversion
While this may seem like a pointless thing to do, it does have practical application. Remember
that gate circuits are signal ampli¯ers, regardless of what logic function they may perform. A weak
signal source (one that is not capable of sourcing or sinking very much current to a load) may be
boosted by means of two inverters like the pair shown in the previous illustration. The logic level is
unchanged, but the full current-sourcing or -sinking capabilities of the ¯nal inverter are available to
drive a load resistance if needed.
For this purpose, a special logic gate called a bu®er is manufactured to perform the same function
as two inverters. Its symbol is simply a triangle, with no inverting "bubble" on the output terminal:
Input Output
"Buffer" gate
Input Output
0
1 1
0
The internal schematic diagram for a typical open-collector bu®er is not much di®erent from
that of a simple inverter: only one more common-emitter transistor stage is added to re-invert the
output signal.
46 CHAPTER 3. LOGIC GATES
Input Output
Vcc
D1
R1 R2
R3
Buffer circuit with open-collector output
Q1 Q2
Q3
Q4
R4
Inverter Inverter
Let's analyze this circuit for two conditions: an input logic level of "1" and an input logic level
of "0." First, a "high" (1) input:
Output
Input
Vcc
D1
R1 R2
R3
Q1 Q2
Q3
Q4
R4
Vcc
As before with the inverter circuit, the "high" input causes no conduction through the left
steering diode of Q1 (emitter-to-base PN junction). All of R1's current goes through the base of
transistor Q2, saturating it:
3.3. THE "BUFFER" GATE 47
Output
Input
Vcc
D1
R1 R2
R3
Q1 Q2
Q3
Q4
R4
Vcc
Having Q2 saturated causes Q3 to be saturated as well, resulting in very little voltage dropped
between the base and emitter of the ¯nal output transistor Q4. Thus, Q4 will be in cuto® mode,
conducting no current. The output terminal will be °oating (neither connected to ground nor Vcc),
and this will be equivalent to a "high" state on the input of the next TTL gate that this one feeds
in to. Thus, a "high" input gives a "high" output.
With a "low" input signal (input terminal grounded), the analysis looks something like this:
Output
Input
Vcc
D1
R1 R2
R3
Q1 Q2
Q3
Q4
R4
Vcc
All of R1's current is now diverted through the input switch, thus eliminating base current
through Q2. This forces transistor Q2 into cuto® so that no base current goes through Q3 either.
With Q3 cuto® as well, Q4 is will be saturated by the current through resistor R4, thus connecting
the output terminal to ground, making it a "low" logic level. Thus, a "low" input gives a "low"
48 CHAPTER 3. LOGIC GATES
output.
The schematic diagram for a bu®er circuit with totem pole output transistors is a bit more
complex, but the basic principles, and certainly the truth table, are the same as for the open-
collector circuit:
Output
Input
Vcc
D1
R1 R2
R3
Q1 Q2
Q3
Buffer circuit with totem pole output
Q4
Q5
Q6
D2
D3
R4
R5
Inverter Inverter
² REVIEW:
² Two inverter, or NOT, gates connected in "series" so as to invert, then re-invert, a binary bit
perform the function of a bu®er. Bu®er gates merely serve the purpose of signal ampli¯cation:
taking a "weak" signal source that isn't capable of sourcing or sinking much current, and
boosting the current capacity of the signal so as to be able to drive a load.
² Bu®er circuits are symbolized by a triangle symbol with no inverter "bubble."
² Bu®ers, like inverters, may be made in open-collector output or totem pole output forms.
3.4 Multiple-input gates
Inverters and bu®ers exhaust the possibilities for single-input gate circuits. What more can be done
with a single logic signal but to bu®er it or invert it? To explore more logic gate possibilities, we
must add more input terminals to the circuit(s).
Adding more input terminals to a logic gate increases the number of input state possibilities.
With a single-input gate such as the inverter or bu®er, there can only be two possible input states:
either the input is "high" (1) or it is "low" (0). As was mentioned previously in this chapter, a two
input gate has four possibilities (00, 01, 10, and 11). A three-input gate has eight possibilities (000,
3.4. MULTIPLE-INPUT GATES 49
001, 010, 011, 100, 101, 110, and 111) for input states. The number of possible input states is equal
to two to the power of the number of inputs:
Number of possible input states = 2n
Where,
n = Number of inputs
This increase in the number of possible input states obviously allows for more complex gate
behavior. Now, instead of merely inverting or amplifying (bu®ering) a single "high" or "low" logic
level, the output of the gate will be determined by whatever combination of 1's and 0's is present
at the input terminals.
Since so many combinations are possible with just a few input terminals, there are many di®erent
types of multiple-input gates, unlike single-input gates which can only be inverters or bu®ers. Each
basic gate type will be presented in this section, showing its standard symbol, truth table, and
practical operation. The actual TTL circuitry of these di®erent gates will be explored in subsequent
sections.
3.4.1 The AND gate
One of the easiest multiple-input gates to understand is the AND gate, so-called because the output
of this gate will be "high" (1) if and only if all inputs (¯rst input and the second input and . . .)
are "high" (1). If any input(s) are "low" (0), the output is guaranteed to be in a "low" state as well.
InputA
InputB
Output
2-input AND gate
Output
3-input AND gate
InputA
InputB
InputC
In case you might have been wondering, AND gates are made with more than three inputs, but
this is less common than the simple two-input variety.
A two-input AND gate's truth table looks like this:
InputA
InputB
Output
2-input AND gate
A B Output
0 0
0 1
1 0
1 1
0
0
0
1
50 CHAPTER 3. LOGIC GATES
What this truth table means in practical terms is shown in the following sequence of illustrations,
with the 2-input AND gate subjected to all possibilities of input logic levels. An LED (Light-Emitting
Diode) provides visual indication of the output logic level:
InputA
InputB
Output
Vcc
Vcc
0
0 0
InputA =
InputB =
Output =
0
0
0 (no light)
InputA
InputB
Output
Vcc
Vcc
0
0
InputA =
InputB =
Output =
0
0 (no light)
1
1
InputA
InputB
Output
Vcc
Vcc
0 0
InputA =
InputB =
Output =
0
0 (no light)
1
1
3.4. MULTIPLE-INPUT GATES 51
InputA
InputB
Output
Vcc
Vcc
InputA =
InputB =
Output =
1
1
1 1
1
1 (light!)
It is only with all inputs raised to "high" logic levels that the AND gate's output goes "high,"
thus energizing the LED for only one out of the four input combination states.
3.4.2 The NAND gate
A variation on the idea of the AND gate is called the NAND gate. The word "NAND" is a verbal
contraction of the words NOT and AND. Essentially, a NAND gate behaves the same as an AND
gate with a NOT (inverter) gate connected to the output terminal. To symbolize this output signal
inversion, the NAND gate symbol has a bubble on the output line. The truth table for a NAND
gate is as one might expect, exactly opposite as that of an AND gate:
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
1
1
2-input NAND gate
InputA
InputB
Output
Equivalent gate circuit
As with AND gates, NAND gates are made with more than two inputs. In such cases, the same
general principle applies: the output will be "low" (0) if and only if all inputs are "high" (1). If any
input is "low" (0), the output will go "high" (1).
52 CHAPTER 3. LOGIC GATES
3.4.3 The OR gate
Our next gate to investigate is the OR gate, so-called because the output of this gate will be "high"
(1) if any of the inputs (¯rst input or the second input or . . .) are "high" (1). The output of an
OR gate goes "low" (0) if and only if all inputs are "low" (0).
InputA
InputB
Output Output
InputA
InputB
InputC
2-input OR gate 3-input OR gate
A two-input OR gate's truth table looks like this:
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1
0
1
2-input OR gate
1
1
The following sequence of illustrations demonstrates the OR gate's function, with the 2-inputs
experiencing all possible logic levels. An LED (Light-Emitting Diode) provides visual indication of
the gate's output logic level:
InputA
InputB
Output
Vcc
Vcc
0
0 0
InputA =
InputB =
Output =
0
0
0 (no light)
3.4. MULTIPLE-INPUT GATES 53
InputA
InputB
Output
Vcc
Vcc
0
InputA =
InputB =
Output =
0
1
1
1
1 (light!)
InputA
InputB
Output
Vcc
Vcc
0
InputA =
InputB =
Output =
0
1
1
1
1 (light!)
InputA
InputB
Output
Vcc
Vcc
InputA =
InputB =
Output =
1
1
1
1 (light!)
1
1
A condition of any input being raised to a "high" logic level makes the OR gate's output go
"high," thus energizing the LED for three out of the four input combination states.
3.4.4 The NOR gate
As you might have suspected, the NOR gate is an OR gate with its output inverted, just like a
NAND gate is an AND gate with an inverted output.
54 CHAPTER 3. LOGIC GATES
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
InputA
InputB
Output
Equivalent gate circuit
2-input NOR gate
0
0
NOR gates, like all the other multiple-input gates seen thus far, can be manufactured with more
than two inputs. Still, the same logical principle applies: the output goes "low" (0) if any of the
inputs are made "high" (1). The output is "high" (1) only when all inputs are "low" (0).
3.4.5 The Negative-AND gate
A Negative-AND gate functions the same as an AND gate with all its inputs inverted (connected
through NOT gates). In keeping with standard gate symbol convention, these inverted inputs are
signi¯ed by bubbles. Contrary to most peoples' ¯rst instinct, the logical behavior of a Negative-AND
gate is not the same as a NAND gate. Its truth table, actually, is identical to a NOR gate:
3.4. MULTIPLE-INPUT GATES 55
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
InputA
InputB
Output
2-input Negative-AND gate
0
0
InputA
InputB
Output
Equivalent gate circuits
3.4.6 The Negative-OR gate
Following the same pattern, a Negative-OR gate functions the same as an OR gate with all its inputs
inverted. In keeping with standard gate symbol convention, these inverted inputs are signi¯ed by
bubbles. The behavior and truth table of a Negative-OR gate is the same as for a NAND gate:
56 CHAPTER 3. LOGIC GATES
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
InputA
InputB
Output
InputA
InputB
Output
Equivalent gate circuits
2-input Negative-OR gate
1
1
3.4.7 The Exclusive-OR gate
The last six gate types are all fairly direct variations on three basic functions: AND, OR, and NOT.
The Exclusive-OR gate, however, is something quite di®erent.
Exclusive-OR gates output a "high" (1) logic level if the inputs are at di®erent logic levels, either
0 and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are at the same
logic levels. The Exclusive-OR (sometimes called XOR) gate has both a symbol and a truth table
pattern that is unique:
3.4. MULTIPLE-INPUT GATES 57
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
1
Exclusive-OR gate
0
There are equivalent circuits for an Exclusive-OR gate made up of AND, OR, and NOT gates,
just as there were for NAND, NOR, and the negative-input gates. A rather direct approach to
simulating an Exclusive-OR gate is to start with a regular OR gate, then add additional gates to
inhibit the output from going "high" (1) when both inputs are "high" (1):
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
1
0
Exclusive-OR equivalent circuit
In this circuit, the ¯nal AND gate acts as a bu®er for the output of the OR gate whenever the
NAND gate's output is high, which it is for the ¯rst three input state combinations (00, 01, and 10).
However, when both inputs are "high" (1), the NAND gate outputs a "low" (0) logic level, which
forces the ¯nal AND gate to produce a "low" (0) output.
Another equivalent circuit for the Exclusive-OR gate uses a strategy of two AND gates with
inverters, set up to generate "high" (1) outputs for input conditions 01 and 10. A ¯nal OR gate
then allows either of the AND gates' "high" outputs to create a ¯nal "high" output:
58 CHAPTER 3. LOGIC GATES
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
1
0
Exclusive-OR equivalent circuit
Exclusive-OR gates are very useful for circuits where two or more binary numbers are to be
compared bit-for-bit, and also for error detection (parity check) and code conversion (binary to
Grey and vice versa).
3.4.8 The Exclusive-NOR gate
Finally, our last gate for analysis is the Exclusive-NOR gate, otherwise known as the XNOR gate.
It is equivalent to an Exclusive-OR gate with an inverted output. The truth table for this gate is
exactly opposite as for the Exclusive-OR gate:
3.5. TTL NAND AND AND GATES 59
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1
1
InputA
InputB
Output
Equivalent gate circuit
0
0
Exclusive-NOR gate
1
As indicated by the truth table, the purpose of an Exclusive-NOR gate is to output a "high" (1)
logic level whenever both inputs are at the same logic levels (either 00 or 11).
² REVIEW:
² Rule for an AND gate: output is "high" only if ¯rst input and second input are both "high."
² Rule for an OR gate: output is "high" if input A or input B are "high."
² Rule for a NAND gate: output is not "high" if both the ¯rst input and the second input are
"high."
² Rule for a NOR gate: output is not "high" if either the ¯rst input or the second input are
"high."
² A Negative-AND gate behaves like a NOR gate.
² A Negative-OR gate behaves like a NAND gate.
² Rule for an Exclusive-OR gate: output is "high" if the input logic levels are di®erent.
² Rule for an Exclusive-NOR gate: output is "high" if the input logic levels are the same.
3.5 TTL NAND and AND gates
Suppose we altered our basic open-collector inverter circuit, adding a second input terminal just like
the ¯rst:
60 CHAPTER 3. LOGIC GATES
Output
Vcc
D1
R1 R2
R3
D2
"Q1"
Q2
Q3
A two-input inverter circuit
InputA
InputB
This schematic illustrates a real circuit, but it isn't called a "two-input inverter." Through
analysis we will discover what this circuit's logic function is and correspondingly what it should be
designated as.
Just as in the case of the inverter and bu®er, the "steering" diode cluster marked "Q1" is actually
formed like a transistor, even though it isn't used in any amplifying capacity. Unfortunately, a simple
NPN transistor structure is inadequate to simulate the three PN junctions necessary in this diode
network, so a di®erent transistor (and symbol) is needed. This transistor has one collector, one base,
and two emitters, and in the circuit it looks like this:
Output
Vcc
D1
R1 R2
R3
D2
Q2
Q3
Q1
InputA
InputB
3.5. TTL NAND AND AND GATES 61
In the single-input (inverter) circuit, grounding the input resulted in an output that assumed the
"high" (1) state. In the case of the open-collector output con¯guration, this "high" state was simply
"°oating." Allowing the input to °oat (or be connected to Vcc) resulted in the output becoming
grounded, which is the "low" or 0 state. Thus, a 1 in resulted in a 0 out, and vice versa.
Since this circuit bears so much resemblance to the simple inverter circuit, the only di®erence
being a second input terminal connected in the same way to the base of transistor Q2, we can say
that each of the inputs will have the same e®ect on the output. Namely, if either of the inputs are
grounded, transistor Q2 will be forced into a condition of cuto®, thus turning Q3 o® and °oating the
output (output goes "high"). The following series of illustrations shows this for three input states
(00, 01, and 10):
Output
Vcc
D1
R1 R2
R3
D2
"Q1"
Q2
Q3
InputA
InputB
Vcc
0
0 Cutoff
Cutoff
1
InputA =
InputB =
Output =
0
0
1
Output
Vcc
D1
R1 R2
R3
D2
"Q1"
Q2
Q3
InputA
InputB
Vcc
0 Cutoff
Cutoff
1
InputA =
InputB =
Output =
0
1
1
1
62 CHAPTER 3. LOGIC GATES
Output
Vcc
D1
R1 R2
R3
D2
"Q1"
Q2
Q3
InputA
InputB
Vcc
0
Cutoff
Cutoff
1
InputA =
InputB =
Output =
0
1
1
1
In any case where there is a grounded ("low") input, the output is guaranteed to be °oating
("high"). Conversely, the only time the output will ever go "low" is if transistor Q3 turns on, which
means transistor Q2 must be turned on (saturated), which means neither input can be diverting R1
current away from the base of Q2. The only condition that will satisfy this requirement is when
both inputs are "high" (1):
Output
Vcc
D1
R1 R2
R3
D2
"Q1"
Q2
Q3
InputA
InputB
Vcc
InputA =
InputB =
Output = 0
1
1
1
Saturation
Saturation
1
0
Collecting and tabulating these results into a truth table, we see that the pattern matches that
of the NAND gate:
3.5. TTL NAND AND AND GATES 63
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
1
1
NAND gate
In the earlier section on NAND gates, this type of gate was created by taking an AND gate
and increasing its complexity by adding an inverter (NOT gate) to the output. However, when we
examine this circuit, we see that the NAND function is actually the simplest, most natural mode of
operation for this TTL design. To create an AND function using TTL circuitry, we need to increase
the complexity of this circuit by adding an inverter stage to the output, just like we had to add an
additional transistor stage to the TTL inverter circuit to turn it into a bu®er:
Output
Vcc
D1
R1 R2
R3
Q1 Q2
Q3
Q4
R4
Inverter
AND gate with open-collector output
NAND gate
D2
InputA
InputB
The truth table and equivalent gate circuit (an inverted-output NAND gate) are shown here:
64 CHAPTER 3. LOGIC GATES
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 1
AND gate
Equivalent circuit
InputA
InputB
Output
0
0
0
Of course, both NAND and AND gate circuits may be designed with totem-pole output stages
rather than open-collector. I am opting to show the open-collector versions for the sake of simplicity.
² REVIEW:
² A TTL NAND gate can be made by taking a TTL inverter circuit and adding another input.
² An AND gate may be created by adding an inverter stage to the output of the NAND gate
circuit.
3.6 TTL NOR and OR gates
Let's examine the following TTL circuit and analyze its operation:
3.6. TTL NOR AND OR GATES 65
Output
Vcc
D1
R1 R2 R3
D2
Q2
Q1 InputA
InputB
Q3 Q4
Q5
R4
Transistors Q1 and Q2 are both arranged in the same manner that we've seen for transistor Q1
in all the other TTL circuits. Rather than functioning as ampli¯ers, Q1 and Q2 are both being used
as two-diode "steering" networks. We may replace Q1 and Q2 with diode sets to help illustrate:
Output
Vcc
D1
R1 R2 R3
D2
InputA
InputB
Q3 Q4
Q5
R4
"Q1"
"Q2"
If input A is left °oating (or connected to Vcc), current will go through the base of transistor Q3,
saturating it. If input A is grounded, that current is diverted away from Q3's base through the left
steering diode of "Q1," thus forcing Q3 into cuto®. The same can be said for input B and transistor
Q4: the logic level of input B determines Q4's conduction: either saturated or cuto®.
Notice how transistors Q3 and Q4 are paralleled at their collector and emitter terminals. In
essence, these two transistors are acting as paralleled switches, allowing current through resistors
R3 and R4 according to the logic levels of inputs A and B. If any input is at a "high" (1) level,
66 CHAPTER 3. LOGIC GATES
then at least one of the two transistors (Q3 and/or Q4) will be saturated, allowing current through
resistors R3 and R4, and turning on the ¯nal output transistor Q5 for a "low" (0) logic level output.
The only way the output of this circuit can ever assume a "high" (1) state is if both Q3 and Q4 are
cuto®, which means both inputs would have to be grounded, or "low" (0).
This circuit's truth table, then, is equivalent to that of the NOR gate:
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
1
NOR gate
0
0
In order to turn this NOR gate circuit into an OR gate, we would have to invert the output logic
level with another transistor stage, just like we did with the NAND-to-AND gate example:
Output
Vcc
D1
R1 R2 R3
D2
Q2
Q1 InputA
InputB
Q3 Q4
Q5
R4
R5
Q6
OR gate with open-collector output
NOR gate Inverter
The truth table and equivalent gate circuit (an inverted-output NOR gate) are shown here:
3.7. CMOS GATE CIRCUITRY 67
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 1
Equivalent circuit
InputA
InputB
Output
0
OR gate
1
1
Of course, totem-pole output stages are also possible in both NOR and OR TTL logic circuits.
² REVIEW:
² An OR gate may be created by adding an inverter stage to the output of the NOR gate circuit.
3.7 CMOS gate circuitry
Up until this point, our analysis of transistor logic circuits has been limited to the TTL design
paradigm, whereby bipolar transistors are used, and the general strategy of °oating inputs being
equivalent to "high" (connected to Vcc) inputs { and correspondingly, the allowance of "open-
collector" output stages { is maintained. This, however, is not the only way we can build logic
gates.
Field-e®ect transistors, particularly the insulated-gate variety, may be used in the design of gate
circuits. Being voltage-controlled rather than current-controlled devices, IGFETs tend to allow very
simple circuit designs. Take for instance, the following inverter circuit built using P- and N-channel
IGFETs:
68 CHAPTER 3. LOGIC GATES
Vdd (+5 volts)
Inverter circuit using IGFETs
Input Output
Notice the "Vdd" label on the positive power supply terminal. This label follows the same
convention as "Vcc" in TTL circuits: it stands for the constant voltage applied to the drain of a
¯eld e®ect transistor, in reference to ground.
Let's connect this gate circuit to a power source and input switch, and examine its operation.
Please note that these IGFET transistors are E-type (Enhancement-mode), and so are normally-o®
devices. It takes an applied voltage between gate and drain (actually, between gate and substrate)
of the correct polarity to bias them on.
Input Output
0 V
5 V
+
-
Saturated
Cutoff
5 V
+
-
5 V
+
-
Input = "low" (0)
Output = "high" (1)
The upper transistor is a P-channel IGFET. When the channel (substrate) is made more positive
than the gate (gate negative in reference to the substrate), the channel is enhanced and current is
allowed between source and drain. So, in the above illustration, the top transistor is turned on.
The lower transistor, having zero voltage between gate and substrate (source), is in its normal
mode: o®. Thus, the action of these two transistors are such that the output terminal of the gate
circuit has a solid connection to Vdd and a very high resistance connection to ground. This makes
the output "high" (1) for the "low" (0) state of the input.
Next, we'll move the input switch to its other position and see what happens:
3.7. CMOS GATE CIRCUITRY 69
Input Output
0 V
5 V
+
-
Saturated
Cutoff
5 V
+
-
0 V
Input = "high" (1)
Output = "low" (0)
Now the lower transistor (N-channel) is saturated because it has su±cient voltage of the correct
polarity applied between gate and substrate (channel) to turn it on (positive on gate, negative on
the channel). The upper transistor, having zero voltage applied between its gate and substrate, is
in its normal mode: o®. Thus, the output of this gate circuit is now "low" (0). Clearly, this circuit
exhibits the behavior of an inverter, or NOT gate.
Using ¯eld-e®ect transistors instead of bipolar transistors has greatly simpli¯ed the design of
the inverter gate. Note that the output of this gate never °oats as is the case with the simplest
TTL circuit: it has a natural "totem-pole" con¯guration, capable of both sourcing and sinking load
current. Key to this gate circuit's elegant design is the complementary use of both P- and N-channel
IGFETs. Since IGFETs are more commonly known as MOSFETs (Metal-Oxide-Semiconductor
Field E®ect Transistor), and this circuit uses both P- and N-channel transistors together, the
general classi¯cation given to gate circuits like this one is CMOS: Complementary Metal Oxide
Semiconductor.
CMOS circuits aren't plagued by the inherent nonlinearities of the ¯eld-e®ect transistors, because
as digital circuits their transistors always operate in either the saturated or cuto® modes and never
in the active mode. Their inputs are, however, sensitive to high voltages generated by electrostatic
(static electricity) sources, and may even be activated into "high" (1) or "low" (0) states by spurious
voltage sources if left °oating. For this reason, it is inadvisable to allow a CMOS logic gate input
to °oat under any circumstances. Please note that this is very di®erent from the behavior of a TTL
gate where a °oating input was safely interpreted as a "high" (1) logic level.
This may cause a problem if the input to a CMOS logic gate is driven by a single-throw switch,
where one state has the input solidly connected to either Vdd or ground and the other state has the
input °oating (not connected to anything):
70 CHAPTER 3. LOGIC GATES
Input
... Output
CMOS gate
When switch is closed, the gate sees a
definite "low" (0) input. However, when
switch is open, the input logic level will
be uncertain because it’s floating.
Also, this problem arises if a CMOS gate input is being driven by an open-collector TTL gate.
Because such a TTL gate's output °oats when it goes "high" (1), the CMOS gate input will be left
in an uncertain state:
Input Output
Vcc
...
TTL gate
...
Input
CMOS gate
Open-collector
Vdd
When the open-collector TTL gate’s output
is "high" (1), the CMOS gate’s input will be
left floating and in an uncertain logic state.
Fortunately, there is an easy solution to this dilemma, one that is used frequently in CMOS
logic circuitry. Whenever a single-throw switch (or any other sort of gate output incapable of both
sourcing and sinking current) is being used to drive a CMOS input, a resistor connected to either
Vdd or ground may be used to provide a stable logic level for the state in which the driving device's
output is °oating. This resistor's value is not critical: 10 k­ is usually su±cient. When used to
provide a "high" (1) logic level in the event of a °oating signal source, this resistor is known as a
pullup resistor :
3.7. CMOS GATE CIRCUITRY 71
Input
... Output
CMOS gate
When switch is closed, the gate sees a
Vdd
Rpullup
definite "low" (0) input. When the switch
is open, Rpullup will provide the connection
to Vdd needed to secure a reliable "high"
logic level for the CMOS gate input.
When such a resistor is used to provide a "low" (0) logic level in the event of a °oating signal
source, it is known as a pulldown resistor. Again, the value for a pulldown resistor is not critical:
Input
... Output
CMOS gate
When switch is closed, the gate sees a
logic level for the CMOS gate input.
Vdd
Rpulldown
is open, Rpulldown will provide the connection
to ground needed to secure a reliable "low"
definite "high" (1) input. When the switch
Because open-collector TTL outputs always sink, never source, current, pullup resistors are
necessary when interfacing such an output to a CMOS gate input:
Vcc
...
TTL gate
...
CMOS gate
Open-collector
Vdd
Vdd
Rpullup
72 CHAPTER 3. LOGIC GATES
Although the CMOS gates used in the preceding examples were all inverters (single-input), the
same principle of pullup and pulldown resistors applies to multiple-input CMOS gates. Of course, a
separate pullup or pulldown resistor will be required for each gate input:
InputA
InputB
InputC
Vdd
Pullup resistors for a 3-input
CMOS AND gate
This brings us to the next question: how do we design multiple-input CMOS gates such as AND,
NAND, OR, and NOR? Not surprisingly, the answer(s) to this question reveal a simplicity of design
much like that of the CMOS inverter over its TTL equivalent.
For example, here is the schematic diagram for a CMOS NAND gate:
Vdd
Output
InputA
InputB
Q1 Q2
Q3
Q4
CMOS NAND gate
Notice how transistors Q1 and Q3 resemble the series-connected complementary pair from the
inverter circuit. Both are controlled by the same input signal (input A), the upper transistor turning
o® and the lower transistor turning on when the input is "high" (1), and vice versa. Notice also how
transistors Q2 and Q4 are similarly controlled by the same input signal (input B), and how they
will also exhibit the same on/o® behavior for the same input logic levels. The upper transistors of
3.7. CMOS GATE CIRCUITRY 73
both pairs (Q1 and Q2) have their source and drain terminals paralleled, while the lower transistors
(Q3 and Q4) are series-connected. What this means is that the output will go "high" (1) if either
top transistor saturates, and will go "low" (0) only if both lower transistors saturate. The following
sequence of illustrations shows the behavior of this NAND gate for all four possibilities of input logic
levels (00, 01, 10, and 11):
Vdd
Output
InputA
InputB
Q1 Q2
Q3
Q4
Vdd
ON ON
OFF
OFF
1
0
0
Vdd
Output
InputA
InputB
Q1 Q2
Q3
Q4
Vdd
ON
OFF
OFF
1
0
1
ON
Vdd
Output
InputA
InputB
Q1 Q2
Q3
Q4
Vdd
ON
OFF
1
0
1 ON
OFF
74 CHAPTER 3. LOGIC GATES
Vdd
Output
InputA
InputB
Q1 Q2
Q3
Q4
Vdd
1 ON
OFF
1
ON
OFF
0
As with the TTL NAND gate, the CMOS NAND gate circuit may be used as the starting point
for the creation of an AND gate. All that needs to be added is another stage of transistors to invert
the output signal:
Vdd
Output
InputA
InputB
Q1 Q2
Q3
Q4
CMOS AND gate
NAND gate Inverter
Q5
Q6
A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its tran-
sistors are di®erently arranged. Instead of two paralleled sourcing (upper) transistors connected to
Vdd and two series-connected sinking (lower) transistors connected to ground, the NOR gate uses
two series-connected sourcing transistors and two parallel-connected sinking transistors like this:
3.7. CMOS GATE CIRCUITRY 75
Vdd
Output
InputA
InputB
Q1
Q2
Q3 Q4
CMOS NOR gate
As with the NAND gate, transistors Q1 and Q3 work as a complementary pair, as do transistors
Q2 and Q4. Each pair is controlled by a single input signal. If either input A or input B are "high"
(1), at least one of the lower transistors (Q3 or Q4) will be saturated, thus making the output "low"
(0). Only in the event of both inputs being "low" (0) will both lower transistors be in cuto® mode
and both upper transistors be saturated, the conditions necessary for the output to go "high" (1).
This behavior, of course, de¯nes the NOR logic function.
The OR function may be built up from the basic NOR gate with the addition of an inverter
stage on the output:
76 CHAPTER 3. LOGIC GATES
Vdd
Output
InputA
InputB
Q1
Q2
Q3 Q4
Q5
Q6
NOR gate Inverter
CMOS OR gate
Since it appears that any gate possible to construct using TTL technology can be duplicated in
CMOS, why do these two "families" of logic design still coexist? The answer is that both TTL and
CMOS have their own unique advantages.
First and foremost on the list of comparisons between TTL and CMOS is the issue of power
consumption. In this measure of performance, CMOS is the unchallenged victor. Because the com-
plementary P- and N-channel MOSFET pairs of a CMOS gate circuit are (ideally) never conducting
at the same time, there is little or no current drawn by the circuit from the Vdd power supply except
for what current is necessary to source current to a load. TTL, on the other hand, cannot function
without some current drawn at all times, due to the biasing requirements of the bipolar transistors
from which it is made.
There is a caveat to this advantage, though. While the power dissipation of a TTL gate remains
rather constant regardless of its operating state(s), a CMOS gate dissipates more power as the
frequency of its input signal(s) rises. If a CMOS gate is operated in a static (unchanging) condition,
it dissipates zero power (ideally). However, CMOS gate circuits draw transient current during every
output state switch from "low" to "high" and vice versa. So, the more often a CMOS gate switches
modes, the more often it will draw current from the Vdd supply, hence greater power dissipation at
greater frequencies.
A CMOS gate also draws much less current from a driving gate output than a TTL gate because
MOSFETs are voltage-controlled, not current-controlled, devices. This means that one gate can
drive many more CMOS inputs than TTL inputs. The measure of how many gate inputs a single
gate output can drive is called fanout.
Another advantage that CMOS gate designs enjoy over TTL is a much wider allowable range
of power supply voltages. Whereas TTL gates are restricted to power supply (Vcc) voltages be-
3.7. CMOS GATE CIRCUITRY 77
tween 4.75 and 5.25 volts, CMOS gates are typically able to operate on any voltage between 3 and
15 volts! The reason behind this disparity in power supply voltages is the respective bias require-
ments of MOSFET versus bipolar junction transistors. MOSFETs are controlled exclusively by gate
voltage (with respect to substrate), whereas BJTs are current-controlled devices. TTL gate circuit
resistances are precisely calculated for proper bias currents assuming a 5 volt regulated power sup-
ply. Any signi¯cant variations in that power supply voltage will result in the transistor bias currents
being incorrect, which then results in unreliable (unpredictable) operation. The only e®ect that
variations in power supply voltage have on a CMOS gate is the voltage de¯nition of a "high" (1)
state. For a CMOS gate operating at 15 volts of power supply voltage (Vdd), an input signal must
be close to 15 volts in order to be considered "high" (1). The voltage threshold for a "low" (0) signal
remains the same: near 0 volts.
One decided disadvantage of CMOS is slow speed, as compared to TTL. The input capacitances
of a CMOS gate are much, much greater than that of a comparable TTL gate { owing to the use of
MOSFETs rather than BJTs { and so a CMOS gate will be slower to respond to a signal transition
(low-to-high or vice versa) than a TTL gate, all other factors being equal. The RC time constant
formed by circuit resistances and the input capacitance of the gate tend to impede the fast rise- and
fall-times of a digital logic level, thereby degrading high-frequency performance.
A strategy for minimizing this inherent disadvantage of CMOS gate circuitry is to "bu®er" the
output signal with additional transistor stages, to increase the overall voltage gain of the device.
This provides a faster-transitioning output voltage (high-to-low or low-to-high) for an input voltage
slowly changing from one logic state to another. Consider this example, of an "unbu®ered" NOR
gate versus a "bu®ered," or B-series, NOR gate:
78 CHAPTER 3. LOGIC GATES
Vdd
Output
InputA
InputB
Q1
Q2
Q3 Q4
"Unbuffered" NOR gate
Vdd
Output
InputA
InputB
Q1
Q2
Q3 Q4
"B-series" (buffered) NOR gate
In essence, the B-series design enhancement adds two inverters to the output of a simple NOR
circuit. This serves no purpose as far as digital logic is concerned, since two cascaded inverters
simply cancel:
3.7. CMOS GATE CIRCUITRY 79
(same as)
(same as)
However, adding these inverter stages to the circuit does serve the purpose of increasing overall
voltage gain, making the output more sensitive to changes in input state, working to overcome the
inherent slowness caused by CMOS gate input capacitance.
² REVIEW:
² CMOS logic gates are made of IGFET (MOSFET) transistors rather than bipolar junction
transistors.
² CMOS gate inputs are sensitive to static electricity. They may be damaged by high voltages,
and they may assume any logic level if left °oating.
² Pullup and pulldown resistors are used to prevent a CMOS gate input from °oating if being
driven by a signal source capable only of sourcing or sinking current.
² CMOS gates dissipate far less power than equivalent TTL gates, but their power dissipation
increases with signal frequency, whereas the power dissipation of a TTL gate is approximately
constant over a wide range of operating conditions.
² CMOS gate inputs draw far less current than TTL inputs, because MOSFETs are voltage-
controlled, not current-controlled, devices.
² CMOS gates are able to operate on a much wider range of power supply voltages than TTL:
typically 3 to 15 volts versus 4.75 to 5.25 volts for TTL.
² CMOS gates tend to have a much lower maximum operating frequency than TTL gates due
to input capacitances caused by the MOSFET gates.
80 CHAPTER 3. LOGIC GATES
² B-series CMOS gates have "bu®ered" outputs to increase voltage gain from input to output,
resulting in faster output response to input signal changes. This helps overcome the inherent
slowness of CMOS gates due to MOSFET input capacitance and the RC time constant thereby
engendered.
3.8 Special-output gates
It is sometimes desirable to have a logic gate that provides both inverted and non-inverted outputs.
For example, a single-input gate that is both a bu®er and an inverter, with a separate output terminal
for each function. Or, a two-input gate that provides both the AND and the NAND functions in a
single circuit. Such gates do exist and they are referred to as complementary output gates.
The general symbology for such a gate is the basic gate ¯gure with a bar and two output lines
protruding from it. An array of complementary gate symbols is shown in the following illustration:
Complementary buffer
Complementary AND gate
Complementary OR gate
Complementary XOR gate
Complementary gates are especially useful in "crowded" circuits where there may not be enough
physical room to mount the additional integrated circuit chips necessary to provide both inverted
and noninverted outputs using standard gates and additional inverters. They are also useful in
applications where a complementary output is necessary from a gate, but the addition of an inverter
would introduce an unwanted time lag in the inverted output relative to the noninverted output.
The internal circuitry of complemented gates is such that both inverted and noninverted outputs
change state at almost exactly the same time:
3.8. SPECIAL-OUTPUT GATES 81
...
... ...
...
Time delay introduced
by the inverter
Complemented gate Standard gate with inverter added
Another type of special gate output is called tristate, because it has the ability to provide three
di®erent output modes: current sinking ("low" logic level), current sourcing ("high"), and °oating
("high-Z," or high-impedance). Tristate outputs are usually found as an optional feature on bu®er
gates. Such gates require an extra input terminal to control the "high-Z" mode, and this input is
usually called the enable.
Input ... Output
+V
Tristate buffer gate
...
Enable
With the enable input held "high" (1), the bu®er acts like an ordinary bu®er with a totem pole
output stage: it is capable of both sourcing and sinking current. However, the output terminal °oats
(goes into "high-Z" mode) if ever the enable input is grounded ("low"), regardless of the data signal's
logic level. In other words, making the enable input terminal "low" (0) e®ectively disconnects the
gate from whatever its output is wired to so that it can no longer have any e®ect.
Tristate bu®ers are marked in schematic diagrams by a triangle character within the gate symbol
like this:
82 CHAPTER 3. LOGIC GATES
Input Output
Tristate buffer symbol
A B Output
0 0
0 1
1 0
1 1
High-Z
High-Z
0
1
Truth table
(A)
Enable (B)
Tristate bu®ers are also made with inverted enable inputs. Such a gate acts normal when the
enable input is "low" (0) and goes into high-Z output mode when the enable input is "high" (1):
Input Output
A B Output
0 0
0 1
1 0
1 1
High-Z
High-Z
0
1
Truth table
Tristate buffer with
inverted enable input
(A)
Enable (B)
One special type of gate known as the bilateral switch uses gate-controlled MOSFET transistors
acting as on/o® switches to switch electrical signals, analog or digital. The "on" resistance of such
a switch is in the range of several hundred ohms, the "o®" resistance being in the range of several
hundred mega-ohms.
Bilateral switches appear in schematics as SPST (Single-Pole, Single-Throw) switches inside of
rectangular boxes, with a control terminal on one of the box's long sides:
3.8. SPECIAL-OUTPUT GATES 83
Control
In/Out In/Out
CMOS bilateral switch
A bilateral switch might be best envisioned as a solid-state (semiconductor) version of an elec-
tromechanical relay: a signal-actuated switch contact that may be used to conduct virtually any
type of electric signal. Of course, being solid-state, the bilateral switch has none of the undesir-
able characteristics of electromechanical relays, such as contact "bouncing," arcing, slow speed, or
susceptibility to mechanical vibration. Conversely, though, they are rather limited in their current-
carrying ability. Additionally, the signal conducted by the "contact" must not exceed the power
supply "rail" voltages powering the bilateral switch circuit.
Four bilateral switches are packaged inside the popular model "4066" integrated circuit:
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Vdd
GND
Quad CMOS bilateral switch
4066
² REVIEW:
² Complementary gates provide both inverted and noninverted output signals, in such a way
that neither one is delayed with respect to the other.
² Tristate gates provide three di®erent output states: high, low, and °oating (High-Z). Such
gates are commanded into their high-impedance output modes by a separate input terminal
called the enable.
² Bilateral switches are MOSFET circuits providing on/o® switching for a variety of electrical
signal types (analog and digital), controlled by logic level voltage signals. In essence, they are
solid-state relays with very low current-handling ability.
84 CHAPTER 3. LOGIC GATES
3.9 Gate universality
NAND and NOR gates possess a special property: they are universal. That is, given enough gates,
either type of gate is able to mimic the operation of any other gate type. For example, it is possible
to build a circuit exhibiting the OR function using three interconnected NAND gates. The ability
for a single gate type to be able to mimic any other gate type is one enjoyed only by the NAND and
the NOR. In fact, digital control systems have been designed around nothing but either NAND or
NOR gates, all the necessary logic functions being derived from collections of interconnected NANDs
or NORs.
As proof of this property, this section will be divided into subsections showing how all the basic
gate types may be formed using only NANDs or only NORs.
3.9.1 Constructing the NOT function
Input Output
0 1
1 0
Input Output
Input
Output
Input
Output
. . . or . . .
Input
Output Output
+V
Input
As you can see, there are two ways to use a NAND gate as an inverter, and two ways to use a NOR
gate as an inverter. Either method works, although connecting TTL inputs together increases the
amount of current loading to the driving gate. For CMOS gates, common input terminals decreases
the switching speed of the gate due to increased input capacitance.
Inverters are the fundamental tool for transforming one type of logic function into another, and
so there will be many inverters shown in the illustrations to follow. In those diagrams, I will only
show one method of inversion, and that will be where the unused NAND gate input is connected to
+V (either Vcc or Vdd, depending on whether the circuit is TTL or CMOS) and where the unused
input for the NOR gate is connected to ground. Bear in mind that the other inversion method
(connecting both NAND or NOR inputs together) works just as well from a logical (1's and 0's)
3.9. GATE UNIVERSALITY 85
point of view, but is undesirable from the practical perspectives of increased current loading for TTL
and increased input capacitance for CMOS.
3.9.2 Constructing the "bu®er" function
Being that it is quite easy to employ NAND and NOR gates to perform the inverter (NOT) function,
it stands to reason that two such stages of gates will result in a bu®er function, where the output is
the same logical state as the input.
Input Output
0
1 1
0
Input Output
Input
Output
+V
+V
Input
Output
3.9.3 Constructing the AND function
To make the AND function from NAND gates, all that is needed is an inverter (NOT) stage on the
output of a NAND gate. This extra inversion "cancels out" the ¯rst N in NAND, leaving the AND
function. It takes a little more work to wrestle the same functionality out of NOR gates, but it can
be done by inverting ("NOT") all of the inputs to a NOR gate.
86 CHAPTER 3. LOGIC GATES
InputA
InputB
Output
2-input AND gate
A B Output
0 0
0 1
1 0
1 1
0
0
0
1
+V
InputA Output
InputB
Output
InputA
InputB
3.9.4 Constructing the NAND function
It would be pointless to show you how to "construct" the NAND function using a NAND gate, since
there is nothing to do. To make a NOR gate perform the NAND function, we must invert all inputs
to the NOR gate as well as the NOR gate's output. For a two-input gate, this requires three more
NOR gates connected as inverters.
3.9. GATE UNIVERSALITY 87
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1 0
Output
InputA
InputB
2-input NAND gate
1
1
1
3.9.5 Constructing the OR function
Inverting the output of a NOR gate (with another NOR gate connected as an inverter) results in
the OR function. The NAND gate, on the other hand, requires inversion of all inputs to mimic the
OR function, just as we needed to invert all inputs of a NOR gate to obtain the AND function.
Remember that inversion of all inputs to a gate results in changing that gate's essential function
from AND to OR (or vice versa), plus an inverted output. Thus, with all inputs inverted, a NAND
behaves as an OR, a NOR behaves as an AND, an AND behaves as a NOR, and an OR behaves as
a NAND. In Boolean algebra, this transformation is referred to as DeMorgan's Theorem, covered in
more detail in a later chapter of this book.
88 CHAPTER 3. LOGIC GATES
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1
0
1
2-input OR gate
1
1
Output
+V
+V
InputA
InputB
InputA
InputB Output
3.9.6 Constructing the NOR function
Much the same as the procedure for making a NOR gate behave as a NAND, we must invert all
inputs and the output to make a NAND gate function as a NOR.
3.10. LOGIC SIGNAL VOLTAGE LEVELS 89
InputA
InputB
Output
A B Output
0 0
0 1
1 0
1 1
1
Output
+V
+V
InputA
InputB
+V
2-input NOR gate
0
0
0
² REVIEW:
² NAND and NOR gates are universal: that is, they have the ability to mimic any type of gate,
if interconnected in su±cient numbers.
3.10 Logic signal voltage levels
Logic gate circuits are designed to input and output only two types of signals: "high" (1) and "low"
(0), as represented by a variable voltage: full power supply voltage for a "high" state and zero
voltage for a "low" state. In a perfect world, all logic circuit signals would exist at these extreme
voltage limits, and never deviate from them (i.e., less than full voltage for a "high," or more than
zero voltage for a "low"). However, in reality, logic signal voltage levels rarely attain these perfect
limits due to stray voltage drops in the transistor circuitry, and so we must understand the signal
level limitations of gate circuits as they try to interpret signal voltages lying somewhere between full
supply voltage and zero.
TTL gates operate on a nominal power supply voltage of 5 volts, +/- 0.25 volts. Ideally, a TTL
"high" signal would be 5.00 volts exactly, and a TTL "low" signal 0.00 volts exactly. However, real
TTL gate circuits cannot output such perfect voltage levels, and are designed to accept "high" and
"low" signals deviating substantially from these ideal values. "Acceptable" input signal voltages
range from 0 volts to 0.8 volts for a "low" logic state, and 2 volts to 5 volts for a "high" logic
state. "Acceptable" output signal voltages (voltage levels guaranteed by the gate manufacturer over
a speci¯ed range of load conditions) range from 0 volts to 0.5 volts for a "low" logic state, and 2.7
volts to 5 volts for a "high" logic state:
90 CHAPTER 3. LOGIC GATES
Low
High
5 V
2 V
0.8 V
0 V
Acceptable TTL gate
input signal levels
5 V
0 V
High
Low
Acceptable TTL gate
output signal levels
Vcc = 5 V
2.7 V
0.5 V
If a voltage signal ranging between 0.8 volts and 2 volts were to be sent into the input of a TTL
gate, there would be no certain response from the gate. Such a signal would be considered uncertain,
and no logic gate manufacturer would guarantee how their gate circuit would interpret such a signal.
As you can see, the tolerable ranges for output signal levels are narrower than for input signal
levels, to ensure that any TTL gate outputting a digital signal into the input of another TTL gate
will transmit voltages acceptable to the receiving gate. The di®erence between the tolerable output
and input ranges is called the noise margin of the gate. For TTL gates, the low-level noise margin
is the di®erence between 0.8 volts and 0.5 volts (0.3 volts), while the high-level noise margin is the
di®erence between 2.7 volts and 2 volts (0.7 volts). Simply put, the noise margin is the peak amount
of spurious or "noise" voltage that may be superimposed on a weak gate output voltage signal before
the receiving gate might interpret it wrongly:
Low
High
5 V
2 V
0.8 V
0 V
Acceptable TTL gate
input signal levels
5 V
0 V
High
Low
Acceptable TTL gate
output signal levels
2.7 V
0.5 V
high-level noise margin
low-level noise margin
CMOS gate circuits have input and output signal speci¯cations that are quite di®erent from
TTL. For a CMOS gate operating at a power supply voltage of 5 volts, the acceptable input signal
voltages range from 0 volts to 1.5 volts for a "low" logic state, and 3.5 volts to 5 volts for a "high"
logic state. "Acceptable" output signal voltages (voltage levels guaranteed by the gate manufacturer
over a speci¯ed range of load conditions) range from 0 volts to 0.05 volts for a "low" logic state, and
4.95 volts to 5 volts for a "high" logic state:
3.10. LOGIC SIGNAL VOLTAGE LEVELS 91
Low
High
5 V
0 V
input signal levels
5 V
0 V
High
Low
output signal levels
Acceptable CMOS gate Acceptable CMOS gate
1.5 V
3.5 V
0.05 V
4.95 V
Vdd = 5 V
It should be obvious from these ¯gures that CMOS gate circuits have far greater noise margins
than TTL: 1.45 volts for CMOS low-level and high-level margins, versus a maximum of 0.7 volts for
TTL. In other words, CMOS circuits can tolerate over twice the amount of superimposed "noise"
voltage on their input lines before signal interpretation errors will result.
CMOS noise margins widen even further with higher operating voltages. Unlike TTL, which is
restricted to a power supply voltage of 5 volts, CMOS may be powered by voltages as high as 15
volts (some CMOS circuits as high as 18 volts). Shown here are the acceptable "high" and "low"
states, for both input and output, of CMOS integrated circuits operating at 10 volts and 15 volts,
respectively:
Low
High
0 V
input signal levels
0 V
High
Low
output signal levels
Acceptable CMOS gate Acceptable CMOS gate
0.05 V
Vdd = 10 V
10 V 10 V
9.95 V
3 V
7 V
92 CHAPTER 3. LOGIC GATES
Low
High
0 V
input signal levels
0 V
High
Low
output signal levels
Acceptable CMOS gate Acceptable CMOS gate
0.05 V
Vdd = 15 V
15 V
14.95 V
15 V
11 V
4 V
The margins for acceptable "high" and "low" signals may be greater than what is shown in the
previous illustrations. What is shown represents "worst-case" input signal performance, based on
manufacturer's speci¯cations. In practice, it may be found that a gate circuit will tolerate "high"
signals of considerably less voltage and "low" signals of considerably greater voltage than those
speci¯ed here.
Conversely, the extremely small output margins shown { guaranteeing output states for "high"
and "low" signals to within 0.05 volts of the power supply "rails" { are optimistic. Such "solid"
output voltage levels will be true only for conditions of minimum loading. If the gate is sourcing or
sinking substantial current to a load, the output voltage will not be able to maintain these optimum
levels, due to internal channel resistance of the gate's ¯nal output MOSFETs.
Within the "uncertain" range for any gate input, there will be some point of demarcation dividing
the gate's actual "low" input signal range from its actual "high" input signal range. That is,
somewhere between the lowest "high" signal voltage level and the highest "low" signal voltage level
guaranteed by the gate manufacturer, there is a threshold voltage at which the gate will actually
switch its interpretation of a signal from "low" or "high" or vice versa. For most gate circuits, this
unspeci¯ed voltage is a single point:
3.10. LOGIC SIGNAL VOLTAGE LEVELS 93
0 V
5 V Vdd = 5 V
Vin
Vout
Typical response of a logic gate
to a variable (analog) input voltage
Time
threshold
In the presence of AC "noise" voltage superimposed on the DC input signal, a single threshold
point at which the gate alters its interpretation of logic level will result in an erratic output:
0 V
5 V Vdd = 5 V
Vin
Vout
Time
threshold
Slowly-changing DC signal with
AC noise superimposed
If this scenario looks familiar to you, it's because you remember a similar problem with (analog)
voltage comparator op-amp circuits. With a single threshold point at which an input causes the
output to switch between "high" and "low" states, the presence of signi¯cant noise will cause erratic
changes in the output:
94 CHAPTER 3. LOGIC GATES
-
+
+V
-V
Vin Vout
AC input
voltage
Square wave
output voltage
DC reference
voltage
Vref
The solution to this problem is a bit of positive feedback introduced into the ampli¯er circuit.
With an op-amp, this is done by connecting the output back around to the noninverting (+) input
through a resistor. In a gate circuit, this entails redesigning the internal gate circuitry, establishing
the feedback inside the gate package rather than through external connections. A gate so designed is
called a Schmitt trigger. Schmitt triggers interpret varying input voltages according to two threshold
voltages: a positive-going threshold (VT+), and a negative-going threshold (VT¡):
0 V
5 V Vdd = 5 V
Vin
Vout
Time
VT+
VTSchmitt
trigger response to a
"noisy" input signal
Schmitt trigger gates are distinguished in schematic diagrams by the small "hysteresis" symbol
drawn within them, reminiscent of the B-H curve for a ferromagnetic material. Hysteresis engendered
by positive feedback within the gate circuitry adds an additional level of noise immunity to the gate's
performance. Schmitt trigger gates are frequently used in applications where noise is expected
on the input signal line(s), and/or where an erratic output would be very detrimental to system
performance.
The di®ering voltage level requirements of TTL and CMOS technology present problems when
3.10. LOGIC SIGNAL VOLTAGE LEVELS 95
the two types of gates are used in the same system. Although operating CMOS gates on the same
5.00 volt power supply voltage required by the TTL gates is no problem, TTL output voltage levels
will not be compatible with CMOS input voltage requirements.
Take for instance a TTL NAND gate outputting a signal into the input of a CMOS inverter gate.
Both gates are powered by the same 5.00 volt supply (Vcc). If the TTL gate outputs a "low" signal
(guaranteed to be between 0 volts and 0.5 volts), it will be properly interpreted by the CMOS gate's
input as a "low" (expecting a voltage between 0 volts and 1.5 volts):
TTL CMOS
Vcc Vdd
5 V
+
-
. . .
. . .
0 V
0.5 V
5 V
TTL
output
CMOS
input
5 V
0 V
1.5 V
TTL output falls within
acceptable limits for
CMOS input
"low"
However, if the TTL gate outputs a "high" signal (guaranteed to be between 5 volts and 2.7
volts), it might not be properly interpreted by the CMOS gate's input as a "high" (expecting a
voltage between 5 volts and 3.5 volts):
96 CHAPTER 3. LOGIC GATES
TTL CMOS
Vcc Vdd
5 V
+
-
. . .
. . .
0 V
5 V
TTL
output
CMOS
input
5 V
0 V
acceptable limits for
CMOS input
"high"
2.7 V
3.5 V
TTL output falls outside of
Given this mismatch, it is entirely possible for the TTL gate to output a valid "high" signal
(valid, that is, according to the standards for TTL) that lies within the "uncertain" range for the
CMOS input, and may be (falsely) interpreted as a "low" by the receiving gate. An easy "¯x" for
this problem is to augment the TTL gate's "high" signal voltage level by means of a pullup resistor:
TTL CMOS
Vcc Vdd
5 V
+
-
. . .
. . .
0 V
5 V
TTL
output CMOS
input
5 V
0 V
3.5 V
Rpullup
TTL "high" output voltage
assisted by Rpullup
Something more than this, though, is required to interface a TTL output with a CMOS input,
if the receiving CMOS gate is powered by a greater power supply voltage:
3.10. LOGIC SIGNAL VOLTAGE LEVELS 97
TTL CMOS
Vcc Vdd
5 V
+
-
. . .
. . .
+
-
10 V
5 V
0 V
10 V
0 V
TTL
output
CMOS
input
3 V
7 V
2.7 V
0.5 V
The TTL "high" signal will
definitely not fall within the
CMOS gate’s acceptable limits
There will be no problem with the CMOS gate interpreting the TTL gate's "low" output, of
course, but a "high" signal from the TTL gate is another matter entirely. The guaranteed output
voltage range of 2.7 volts to 5 volts from the TTL gate output is nowhere near the CMOS gate's
acceptable range of 7 volts to 10 volts for a "high" signal. If we use an open-collector TTL gate
instead of a totem-pole output gate, though, a pullup resistor to the 10 volt Vdd supply rail will
raise the TTL gate's "high" output voltage to the full power supply voltage supplying the CMOS
gate. Since an open-collector gate can only sink current, not source current, the "high" state voltage
level is entirely determined by the power supply to which the pullup resistor is attached, thus neatly
solving the mismatch problem:
98 CHAPTER 3. LOGIC GATES
TTL CMOS
Vcc Vdd
5 V
+
-
. . .
. . .
+
-
10 V
0 V
10 V
0 V
TTL
output
CMOS
input
3 V
7 V
0.5 V
Rpullup
10 V
Now, both "low" and "high"
TTL signals are acceptable
to the CMOS gate input
(open-collector)
Due to the excellent output voltage characteristics of CMOS gates, there is typically no problem
connecting a CMOS output to a TTL input. The only signi¯cant issue is the current loading
presented by the TTL inputs, since the CMOS output must sink current for each of the TTL inputs
while in the "low" state.
When the CMOS gate in question is powered by a voltage source in excess of 5 volts (Vcc),
though, a problem will result. The "high" output state of the CMOS gate, being greater than 5
volts, will exceed the TTL gate's acceptable input limits for a "high" signal. A solution to this
problem is to create an "open-collector" inverter circuit using a discrete NPN transistor, and use it
to interface the two gates together:
CMOS TTL
Vcc Vdd
5 V
+
-
. . .
. . .
+
-
10 V
Rpullup
The "Rpullup" resistor is optional, since TTL inputs automatically assume a "high" state when
left °oating, which is what will happen when the CMOS gate output is "low" and the transistor cuts
o®. Of course, one very important consequence of implementing this solution is the logical inversion
created by the transistor: when the CMOS gate outputs a "low" signal, the TTL gate sees a "high"
input; and when the CMOS gate outputs a "high" signal, the transistor saturates and the TTL gate
sees a "low" input. So long as this inversion is accounted for in the logical scheme of the system, all
will be well.
3.11. DIP GATE PACKAGING 99
3.11 DIP gate packaging
Digital logic gate circuits are manufactured as integrated circuits: all the constituent transistors and
resistors built on a single piece of semiconductor material. The engineer, technician, or hobbyist
using small numbers of gates will likely ¯nd what he or she needs enclosed in a DIP (Dual Inline
Package) housing. DIP-enclosed integrated circuits are available with even numbers of pins, located
at 0.100 inch intervals from each other for standard circuit board layout compatibility. Pin counts
of 8, 14, 16, 18, and 24 are common for DIP "chips."
Part numbers given to these DIP packages specify what type of gates are enclosed, and how many.
These part numbers are industry standards, meaning that a "74LS02" manufactured by Motorola
will be identical in function to a "74LS02" manufactured by Fairchild or by any other manufacturer.
Letter codes prepended to the part number are unique to the manufacturer, and are not industry-
standard codes. For instance, a SN74LS02 is a quad 2-input TTL NOR gate manufactured by
Motorola, while a DM74LS02 is the exact same circuit manufactured by Fairchild.
Logic circuit part numbers beginning with "74" are commercial-grade TTL. If the part number
begins with the number "54", the chip is a military-grade unit: having a greater operating tem-
perature range, and typically more robust in regard to allowable power supply and signal voltage
levels. The letters "LS" immediately following the 74/54 pre¯x indicate "Low-power Schottky"
circuitry, using Schottky-barrier diodes and transistors throughout, to decrease power dissipation.
Non-Schottky gate circuits consume more power, but are able to operate at higher frequencies due
to their faster switching times.
A few of the more common TTL "DIP" circuit packages are shown here for reference:
100 CHAPTER 3. LOGIC GATES
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Vcc
GND
Quad NAND gate
5400/7400
Vcc
GND
14 13 12 11 10 9 8
1 2 3 4 5 6 7
5402/7402
Quad NOR gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Vcc
GND
5408/7408
Quad AND gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Vcc
GND
5432/7432
Quad OR gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Vcc
GND
5486/7486
Quad XOR gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Vcc
GND
5404/7404
Hex inverter
3.12. CONTRIBUTORS 101
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
Quad NAND gate
GND
14 13 12 11 10 9 8
1 2 3 4 5 6 7
Quad NOR gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
Quad AND gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
Quad OR gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
Quad XOR gate
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
Hex inverter
4011
Vdd Vdd
Vdd Vdd
Vdd Vdd
4001
4081 4071
4070 4069
3.12 Contributors
Contributors to this chapter are listed in chronological order of their contributions, from most recent
to ¯rst. See Appendix 2 (Contributor List) for dates and contact information.
Jan-Willem Rensman (May 2, 2002): Suggested the inclusion of Schmitt triggers and gate
hysteresis to this chapter.
102 CHAPTER 3. LOGIC GATES
Chapter 4
SWITCHES
Contents
4.1 Switch types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2 Switch contact design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3 Contact "normal" state and make/break sequence . . . . . . . . . . . 111
4.4 Contact "bounce" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.1 Switch types
An electrical switch is any device used to interrupt the °ow of electrons in a circuit. Switches
are essentially binary devices: they are either completely on ("closed") or completely o® ("open").
There are many di®erent types of switches, and we will explore some of these types in this chapter.
Though it may seem strange to cover this elementary electrical topic at such a late stage in this
book series, I do so because the chapters that follow explore an older realm of digital technology based
on mechanical switch contacts rather than solid-state gate circuits, and a thorough understanding of
switch types is necessary for the undertaking. Learning the function of switch-based circuits at the
same time that you learn about solid-state logic gates makes both topics easier to grasp, and sets
the stage for an enhanced learning experience in Boolean algebra, the mathematics behind digital
logic circuits.
The simplest type of switch is one where two electrical conductors are brought in contact with
each other by the motion of an actuating mechanism. Other switches are more complex, containing
electronic circuits able to turn on or o® depending on some physical stimulus (such as light or
magnetic ¯eld) sensed. In any case, the ¯nal output of any switch will be (at least) a pair of
wire-connection terminals that will either be connected together by the switch's internal contact
mechanism ("closed"), or not connected together ("open").
Any switch designed to be operated by a person is generally called a hand switch, and they are
manufactured in several varieties:
103
104 CHAPTER 4. SWITCHES
Toggle switch
Toggle switches are actuated by a lever angled in one of two or more positions. The common
light switch used in household wiring is an example of a toggle switch. Most toggle switches will
come to rest in any of their lever positions, while others have an internal spring mechanism returning
the lever to a certain normal position, allowing for what is called "momentary" operation.
Pushbutton switch
Pushbutton switches are two-position devices actuated with a button that is pressed and released.
Most pushbutton switches have an internal spring mechanism returning the button to its "out," or
"unpressed," position, for momentary operation. Some pushbutton switches will latch alternately on
or o® with every push of the button. Other pushbutton switches will stay in their "in," or "pressed,"
position until the button is pulled back out. This last type of pushbutton switches usually have a
mushroom-shaped button for easy push-pull action.
Selector switch
Selector switches are actuated with a rotary knob or lever of some sort to select one of two or
more positions. Like the toggle switch, selector switches can either rest in any of their positions or
contain spring-return mechanisms for momentary operation.
Joystick switch
A joystick switch is actuated by a lever free to move in more than one axis of motion. One or
more of several switch contact mechanisms are actuated depending on which way the lever is pushed,
and sometimes by how far it is pushed. The circle-and-dot notation on the switch symbol represents
the direction of joystick lever motion required to actuate the contact. Joystick hand switches are
commonly used for crane and robot control.
Some switches are speci¯cally designed to be operated by the motion of a machine rather than by
the hand of a human operator. These motion-operated switches are commonly called limit switches,
because they are often used to limit the motion of a machine by turning o® the actuating power to
a component if it moves too far. As with hand switches, limit switches come in several varieties:
Lever actuator limit switch
4.1. SWITCH TYPES 105
These limit switches closely resemble rugged toggle or selector hand switches ¯tted with a lever
pushed by the machine part. Often, the levers are tipped with a small roller bearing, preventing the
lever from being worn o® by repeated contact with the machine part.
prox
Proximity switch
Proximity switches sense the approach of a metallic machine part either by a magnetic or high-
frequency electromagnetic ¯eld. Simple proximity switches use a permanent magnet to actuate a
sealed switch mechanism whenever the machine part gets close (typically 1 inch or less). More com-
plex proximity switches work like a metal detector, energizing a coil of wire with a high-frequency
current, and electronically monitoring the magnitude of that current. If a metallic part (not nec-
essarily magnetic) gets close enough to the coil, the current will increase, and trip the monitoring
circuit. The symbol shown here for the proximity switch is of the electronic variety, as indicated by
the diamond-shaped box surrounding the switch. A non-electronic proximity switch would use the
same symbol as the lever-actuated limit switch.
Another form of proximity switch is the optical switch, comprised of a light source and photocell.
Machine position is detected by either the interruption or re°ection of a light beam. Optical switches
are also useful in safety applications, where beams of light can be used to detect personnel entry
into a dangerous area.
In many industrial processes, it is necessary to monitor various physical quantities with switches.
Such switches can be used to sound alarms, indicating that a process variable has exceeded normal
parameters, or they can be used to shut down processes or equipment if those variables have reached
dangerous or destructive levels. There are many di®erent types of process switches:
Speed switch
These switches sense the rotary speed of a shaft either by a centrifugal weight mechanism mounted
on the shaft, or by some kind of non-contact detection of shaft motion such as optical or magnetic.
Pressure switch
Gas or liquid pressure can be used to actuate a switch mechanism if that pressure is applied to
a piston, diaphragm, or bellows, which converts pressure to mechanical force.
Temperature switch
106 CHAPTER 4. SWITCHES
An inexpensive temperature-sensing mechanism is the "bimetallic strip:" a thin strip of two
metals, joined back-to-back, each metal having a di®erent rate of thermal expansion. When the
strip heats or cools, di®ering rates of thermal expansion between the two metals causes it to bend.
The bending of the strip can then be used to actuate a switch contact mechanism. Other temperature
switches use a brass bulb ¯lled with either a liquid or gas, with a tiny tube connecting the bulb to
a pressure-sensing switch. As the bulb is heated, the gas or liquid expands, generating a pressure
increase which then actuates the switch mechanism.
Liquid level switch
A °oating object can be used to actuate a switch mechanism when the liquid level in an tank
rises past a certain point. If the liquid is electrically conductive, the liquid itself can be used as a
conductor to bridge between two metal probes inserted into the tank at the required depth. The
conductivity technique is usually implemented with a special design of relay triggered by a small
amount of current through the conductive liquid. In most cases it is impractical and dangerous to
switch the full load current of the circuit through a liquid.
Level switches can also be designed to detect the level of solid materials such as wood chips,
grain, coal, or animal feed in a storage silo, bin, or hopper. A common design for this application
is a small paddle wheel, inserted into the bin at the desired height, which is slowly turned by a
small electric motor. When the solid material ¯lls the bin to that height, the material prevents
the paddle wheel from turning. The torque response of the small motor than trips the switch
mechanism. Another design uses a "tuning fork" shaped metal prong, inserted into the bin from
the outside at the desired height. The fork is vibrated at its resonant frequency by an electronic
circuit and magnet/electromagnet coil assembly. When the bin ¯lls to that height, the solid material
dampens the vibration of the fork, the change in vibration amplitude and/or frequency detected by
the electronic circuit.
Liquid flow switch
Inserted into a pipe, a °ow switch will detect any gas or liquid °ow rate in excess of a certain
threshold, usually with a small paddle or vane which is pushed by the °ow. Other °ow switches are
constructed as di®erential pressure switches, measuring the pressure drop across a restriction built
into the pipe.
Another type of level switch, suitable for liquid or solid material detection, is the nuclear switch.
Composed of a radioactive source material and a radiation detector, the two are mounted across
the diameter of a storage vessel for either solid or liquid material. Any height of material beyond
the level of the source/detector arrangement will attenuate the strength of radiation reaching the
detector. This decrease in radiation at the detector can be used to trigger a relay mechanism to
provide a switch contact for measurement, alarm point, or even control of the vessel level.
4.2. SWITCH CONTACT DESIGN 107
source
source
detector
detector
Nuclear level switch
(for solid or liquid material)
Both source and detector are outside of the vessel, with no intrusion at all except the radiation
°ux itself. The radioactive sources used are fairly weak and pose no immediate health threat to
operations or maintenance personnel.
As usual, there is usually more than one way to implement a switch to monitor a physical process
or serve as an operator control. There is usually no single "perfect" switch for any application,
although some obviously exhibit certain advantages over others. Switches must be intelligently
matched to the task for e±cient and reliable operation.
² REVIEW:
² A switch is an electrical device, usually electromechanical, used to control continuity between
two points.
² Hand switches are actuated by human touch.
² Limit switches are actuated by machine motion.
² Process switches are actuated by changes in some physical process (temperature, level, °ow,
etc.).
4.2 Switch contact design
A switch can be constructed with any mechanism bringing two conductors into contact with each
other in a controlled manner. This can be as simple as allowing two copper wires to touch each
other by the motion of a lever, or by directly pushing two metal strips into contact. However, a good
switch design must be rugged and reliable, and avoid presenting the operator with the possibility of
electric shock. Therefore, industrial switch designs are rarely this crude.
The conductive parts in a switch used to make and break the electrical connection are called
contacts. Contacts are typically made of silver or silver-cadmium alloy, whose conductive properties
are not signi¯cantly compromised by surface corrosion or oxidation. Gold contacts exhibit the best
108 CHAPTER 4. SWITCHES
corrosion resistance, but are limited in current-carrying capacity and may "cold weld" if brought
together with high mechanical force. Whatever the choice of metal, the switch contacts are guided
by a mechanism ensuring square and even contact, for maximum reliability and minimum resistance.
Contacts such as these can be constructed to handle extremely large amounts of electric current,
up to thousands of amps in some cases. The limiting factors for switch contact ampacity are as
follows:
² Heat generated by current through metal contacts (while closed).
² Sparking caused when contacts are opened or closed.
² The voltage across open switch contacts (potential of current jumping across the gap).
One major disadvantage of standard switch contacts is the exposure of the contacts to the
surrounding atmosphere. In a nice, clean, control-room environment, this is generally not a problem.
However, most industrial environments are not this benign. The presence of corrosive chemicals
in the air can cause contacts to deteriorate and fail prematurely. Even more troublesome is the
possibility of regular contact sparking causing °ammable or explosive chemicals to ignite.
When such environmental concerns exist, other types of contacts can be considered for small
switches. These other types of contacts are sealed from contact with the outside air, and therefore
do not su®er the same exposure problems that standard contacts do.
A common type of sealed-contact switch is the mercury switch. Mercury is a metallic element,
liquid at room temperature. Being a metal, it possesses excellent conductive properties. Being
a liquid, it can be brought into contact with metal probes (to close a circuit) inside of a sealed
chamber simply by tilting the chamber so that the probes are on the bottom. Many industrial
switches use small glass tubes containing mercury which are tilted one way to close the contact,
and tilted another way to open. Aside from the problems of tube breakage and spilling mercury
(which is a toxic material), and susceptibility to vibration, these devices are an excellent alternative
to open-air switch contacts wherever environmental exposure problems are a concern.
Here, a mercury switch (often called a tilt switch) is shown in the open position, where the
mercury is out of contact with the two metal contacts at the other end of the glass bulb:
4.2. SWITCH CONTACT DESIGN 109
Here, the same switch is shown in the closed position. Gravity now holds the liquid mercury in
contact with the two metal contacts, providing electrical continuity from one to the other:
Mercury switch contacts are impractical to build in large sizes, and so you will typically ¯nd
such contacts rated at no more than a few amps, and no more than 120 volts. There are exceptions,
of course, but these are common limits.
Another sealed-contact type of switch is the magnetic reed switch. Like the mercury switch,
a reed switch's contacts are located inside a sealed tube. Unlike the mercury switch which uses
liquid metal as the contact medium, the reed switch is simply a pair of very thin, magnetic, metal
strips (hence the name "reed") which are brought into contact with each other by applying a strong
magnetic ¯eld outside the sealed tube. The source of the magnetic ¯eld in this type of switch
is usually a permanent magnet, moved closer to or further away from the tube by the actuating
mechanism. Due to the small size of the reeds, this type of contact is typically rated at lower
currents and voltages than the average mercury switch. However, reed switches typically handle
vibration better than mercury contacts, because there is no liquid inside the tube to splash around.
It is common to ¯nd general-purpose switch contact voltage and current ratings to be greater
on any given switch or relay if the electric power being switched is AC instead of DC. The reason
for this is the self-extinguishing tendency of an alternating-current arc across an air gap. Because
60 Hz power line current actually stops and reverses direction 120 times per second, there are many
opportunities for the ionized air of an arc to lose enough temperature to stop conducting current,
to the point where the arc will not re-start on the next voltage peak. DC, on the other hand, is a
continuous, uninterrupted °ow of electrons which tends to maintain an arc across an air gap much
better. Therefore, switch contacts of any kind incur more wear when switching a given value of direct
current than for the same value of alternating current. The problem of switching DC is exaggerated
when the load has a signi¯cant amount of inductance, as there will be very high voltages generated
across the switch's contacts when the circuit is opened (the inductor doing its best to maintain
circuit current at the same magnitude as when the switch was closed).
With both AC and DC, contact arcing can be minimized with the addition of a "snubber" circuit
(a capacitor and resistor wired in series) in parallel with the contact, like this:
110 CHAPTER 4. SWITCHES
R C
"Snubber"
A sudden rise in voltage across the switch contact caused by the contact opening will be tem-
pered by the capacitor's charging action (the capacitor opposing the increase in voltage by drawing
current). The resistor limits the amount of current that the capacitor will discharge through the
contact when it closes again. If the resistor were not there, the capacitor might actually make the
arcing during contact closure worse than the arcing during contact opening without a capacitor!
While this addition to the circuit helps mitigate contact arcing, it is not without disadvantage: a
prime consideration is the possibility of a failed (shorted) capacitor/resistor combination providing
a path for electrons to °ow through the circuit at all times, even when the contact is open and cur-
rent is not desired. The risk of this failure, and the severity of the resulting consequences must be
considered against the increased contact wear (and inevitable contact failure) without the snubber
circuit.
The use of snubbers in DC switch circuits is nothing new: automobile manufacturers have been
doing this for years on engine ignition systems, minimizing the arcing across the switch contact
"points" in the distributor with a small capacitor called a condenser. As any mechanic can tell
you, the service life of the distributor's "points" is directly related to how well the condenser is
functioning.
With all this discussion concerning the reduction of switch contact arcing, one might be led to
think that less current is always better for a mechanical switch. This, however, is not necessarily
so. It has been found that a small amount of periodic arcing can actually be good for the switch
contacts, because it keeps the contact faces free from small amounts of dirt and corrosion. If a
mechanical switch contact is operated with too little current, the contacts will tend to accumulate
excessive resistance and may fail prematurely! This minimum amount of electric current necessary
to keep a mechanical switch contact in good health is called the wetting current.
Normally, a switch's wetting current rating is far below its maximum current rating, and well
below its normal operating current load in a properly designed system. However, there are applica-
tions where a mechanical switch contact may be required to routinely handle currents below normal
wetting current limits (for instance, if a mechanical selector switch needs to open or close a digital
logic or analog electronic circuit where the current value is extremely small). In these applications,
is it highly recommended that gold-plated switch contacts be speci¯ed. Gold is a "noble" metal and
does not corrode as other metals will. Such contacts have extremely low wetting current require-
ments as a result. Normal silver or copper alloy contacts will not provide reliable operation if used
in such low-current service!
² REVIEW:
² The parts of a switch responsible for making and breaking electrical continuity are called the
"contacts." Usually made of corrosion-resistant metal alloy, contacts are made to touch each
other by a mechanism which helps maintain proper alignment and spacing.
² Mercury switches use a slug of liquid mercury metal as a moving contact. Sealed in a glass
4.3. CONTACT "NORMAL" STATE AND MAKE/BREAK SEQUENCE 111
tube, the mercury contact's spark is sealed from the outside environment, making this type of
switch ideally suited for atmospheres potentially harboring explosive vapors.
² Reed switches are another type of sealed-contact device, contact being made by two thin metal
"reeds" inside a glass tube, brought together by the in°uence of an external magnetic ¯eld.
² Switch contacts su®er greater duress switching DC than AC. This is primarily due to the
self-extinguishing nature of an AC arc.
² A resistor-capacitor network called a "snubber" can be connected in parallel with a switch
contact to reduce contact arcing.
² Wetting current is the minimum amount of electric current necessary for a switch contact to
carry in order for it to be self-cleaning. Normally this value is far below the switch's maximum
current rating.
4.3 Contact "normal" state and make/break sequence
Any kind of switch contact can be designed so that the contacts "close" (establish continuity) when
actuated, or "open" (interrupt continuity) when actuated. For switches that have a spring-return
mechanism in them, the direction that the spring returns it to with no applied force is called the
normal position. Therefore, contacts that are open in this position are called normally open and
contacts that are closed in this position are called normally closed.
For process switches, the normal position, or state, is that which the switch is in when there is
no process in°uence on it. An easy way to ¯gure out the normal condition of a process switch is to
consider the state of the switch as it sits on a storage shelf, uninstalled. Here are some examples of
"normal" process switch conditions:
² Speed switch: Shaft not turning
² Pressure switch: Zero applied pressure
² Temperature switch: Ambient (room) temperature
² Level switch: Empty tank or bin
² Flow switch: Zero liquid °ow
It is important to di®erentiate between a switch's "normal" condition and its "normal" use in an
operating process. Consider the example of a liquid °ow switch that serves as a low-°ow alarm in a
cooling water system. The normal, or properly-operating, condition of the cooling water system is
to have fairly constant coolant °ow going through this pipe. If we want the °ow switch's contact to
close in the event of a loss of coolant °ow (to complete an electric circuit which activates an alarm
siren, for example), we would want to use a °ow switch with normally-closed rather than normally-
open contacts. When there's adequate °ow through the pipe, the switch's contacts are forced open;
when the °ow rate drops to an abnormally low level, the contacts return to their normal (closed)
state. This is confusing if you think of "normal" as being the regular state of the process, so be sure
to always think of a switch's "normal" state as that which it's in as it sits on a shelf.
112 CHAPTER 4. SWITCHES
The schematic symbology for switches vary according to the switch's purpose and actuation. A
normally-open switch contact is drawn in such a way as to signify an open connection, ready to close
when actuated. Conversely, a normally-closed switch is drawn as a closed connection which will be
opened when actuated. Note the following symbols:
Pushbutton switch
Normally-open Normally-closed
There is also a generic symbology for any switch contact, using a pair of vertical lines to represent
the contact points in a switch. Normally-open contacts are designated by the lines not touching,
while normally-closed contacts are designated with a diagonal line bridging between the two lines.
Compare the two:
Normally-open Normally-closed
Generic switch contact designation
The switch on the left will close when actuated, and will be open while in the "normal" (unac-
tuated) position. The switch on the right will open when actuated, and is closed in the "normal"
(unactuated) position. If switches are designated with these generic symbols, the type of switch
usually will be noted in text immediately beside the symbol. Please note that the symbol on the left
is not to be confused with that of a capacitor. If a capacitor needs to be represented in a control
logic schematic, it will be shown like this:
Capacitor
In standard electronic symbology, the ¯gure shown above is reserved for polarity-sensitive capac-
itors. In control logic symbology, this capacitor symbol is used for any type of capacitor, even when
the capacitor is not polarity sensitive, so as to clearly distinguish it from a normally-open switch
contact.
With multiple-position selector switches, another design factor must be considered: that is, the
sequence of breaking old connections and making new connections as the switch is moved from
position to position, the moving contact touching several stationary contacts in sequence.
common
1
2
3
4
5
4.3. CONTACT "NORMAL" STATE AND MAKE/BREAK SEQUENCE 113
The selector switch shown above switches a common contact lever to one of ¯ve di®erent positions,
to contact wires numbered 1 through 5. The most common con¯guration of a multi-position switch
like this is one where the contact with one position is broken before the contact with the next position
is made. This con¯guration is called break-before-make. To give an example, if the switch were set
at position number 3 and slowly turned clockwise, the contact lever would move o® of the number
3 position, opening that circuit, move to a position between number 3 and number 4 (both circuit
paths open), and then touch position number 4, closing that circuit.
There are applications where it is unacceptable to completely open the circuit attached to the
"common" wire at any point in time. For such an application, a make-before-break switch design
can be built, in which the movable contact lever actually bridges between two positions of contact
(between number 3 and number 4, in the above scenario) as it travels between positions. The
compromise here is that the circuit must be able to tolerate switch closures between adjacent position
contacts (1 and 2, 2 and 3, 3 and 4, 4 and 5) as the selector knob is turned from position to position.
Such a switch is shown here:
common
1
2
3
4
5
When movable contact(s) can be brought into one of several positions with stationary contacts,
those positions are sometimes called throws. The number of movable contacts is sometimes called
poles. Both selector switches shown above with one moving contact and ¯ve stationary contacts
would be designated as "single-pole, ¯ve-throw" switches.
If two identical single-pole, ¯ve-throw switches were mechanically ganged together so that they
were actuated by the same mechanism, the whole assembly would be called a "double-pole, ¯ve-
throw" switch:
114 CHAPTER 4. SWITCHES
Double-pole, 5-throw switch
assembly
Here are a few common switch con¯gurations and their abbreviated designations:
Single-pole, single-throw
(SPST)
Double-pole, single-throw
(DPST)
Single-pole, double-throw
(SPDT)
Double-pole, double-throw
(DPDT)
4.4. CONTACT "BOUNCE" 115
Four-pole, double-throw
(4PDT)
² REVIEW:
² The normal state of a switch is that where it is unactuated. For process switches, this is the
condition it's in when sitting on a shelf, uninstalled.
² A switch that is open when unactuated is called normally-open. A switch that is closed when
unactuated is called normally-closed. Sometimes the terms "normally-open" and "normally-
closed" are abbreviated N.O. and N.C., respectively.
² The generic symbology for N.O. and N.C. switch contacts is as follows:
²
Normally-open Normally-closed
Generic switch contact designation
² Multiposition switches can be either break-before-make (most common) or make-before-break.
² The "poles" of a switch refers to the number of moving contacts, while the "throws" of a switch
refers to the number of stationary contacts per moving contact.
4.4 Contact "bounce"
When a switch is actuated and contacts touch one another under the force of actuation, they are
supposed to establish continuity in a single, crisp moment. Unfortunately, though, switches do not
exactly achieve this goal. Due to the mass of the moving contact and any elasticity inherent in the
mechanism and/or contact materials, contacts will "bounce" upon closure for a period of milliseconds
before coming to a full rest and providing unbroken contact. In many applications, switch bounce is
of no consequence: it matters little if a switch controlling an incandescent lamp "bounces" for a few
cycles every time it is actuated. Since the lamp's warm-up time greatly exceeds the bounce period,
no irregularity in lamp operation will result.
However, if the switch is used to send a signal to an electronic ampli¯er or some other circuit
with a fast response time, contact bounce may produce very noticeable and undesired e®ects:
116 CHAPTER 4. SWITCHES
Switch
actuated
A closer look at the oscilloscope display reveals a rather ugly set of makes and breaks when the
switch is actuated a single time:
Close-up view of oscilloscope display:
Switch is actuated
Contacts bouncing
If, for example, this switch is used to provide a "clock" signal to a digital counter circuit, so that
each actuation of the pushbutton switch is supposed to increment the counter by a value of 1, what
will happen instead is the counter will increment by several counts each time the switch is actuated.
Since mechanical switches often interface with digital electronic circuits in modern systems, switch
contact bounce is a frequent design consideration. Somehow, the "chattering" produced by bouncing
contacts must be eliminated so that the receiving circuit sees a clean, crisp o®/on transition:
Switch is actuated
"Bounceless" switch operation
Switch contacts may be debounced several di®erent ways. The most direct means is to address the
4.4. CONTACT "BOUNCE" 117
problem at its source: the switch itself. Here are some suggestions for designing switch mechanisms
for minimum bounce:
² Reduce the kinetic energy of the moving contact. This will reduce the force of impact as it
comes to rest on the stationary contact, thus minimizing bounce.
² Use "bu®er springs" on the stationary contact(s) so that they are free to recoil and gently
absorb the force of impact from the moving contact.
² Design the switch for "wiping" or "sliding" contact rather than direct impact. "Knife" switch
designs use sliding contacts.
² Dampen the switch mechanism's movement using an air or oil "shock absorber" mechanism.
² Use sets of contacts in parallel with each other, each slightly di®erent in mass or contact gap,
so that when one is rebounding o® the stationary contact, at least one of the others will still
be in ¯rm contact.
² "Wet" the contacts with liquid mercury in a sealed environment. After initial contact is made,
the surface tension of the mercury will maintain circuit continuity even though the moving
contact may bounce o® the stationary contact several times.
Each one of these suggestions sacri¯ces some aspect of switch performance for limited bounce,
and so it is impractical to design all switches with limited contact bounce in mind. Alterations made
to reduce the kinetic energy of the contact may result in a small open-contact gap or a slow-moving
contact, which limits the amount of voltage the switch may handle and the amount of current it
may interrupt. Sliding contacts, while non-bouncing, still produce "noise" (irregular current caused
by irregular contact resistance when moving), and su®er from more mechanical wear than normal
contacts.
Multiple, parallel contacts give less bounce, but only at greater switch complexity and cost. Using
mercury to "wet" the contacts is a very e®ective means of bounce mitigation, but it is unfortunately
limited to switch contacts of low ampacity. Also, mercury-wetted contacts are usually limited in
mounting position, as gravity may cause the contacts to "bridge" accidently if oriented the wrong
way.
If re-designing the switch mechanism is not an option, mechanical switch contacts may be de-
bounced externally, using other circuit components to condition the signal. A low-pass ¯lter circuit
attached to the output of the switch, for example, will reduce the voltage/current °uctuations gen-
erated by contact bounce:
118 CHAPTER 4. SWITCHES
Switch
actuated
C
Switch contacts may be debounced electronically, using hysteretic transistor circuits (circuits
that "latch" in either a high or a low state) with built-in time delays (called "one-shot" circuits), or
two inputs controlled by a double-throw switch. These hysteretic circuits, called multivibrators, are
discussed in detail in a later chapter.
Chapter 5
ELECTROMECHANICAL
RELAYS
Contents
5.1 Relay construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2 Contactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3 Time-delay relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.4 Protective relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.5 Solid-state relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1 Relay construction
An electric current through a conductor will produce a magnetic ¯eld at right angles to the direction
of electron °ow. If that conductor is wrapped into a coil shape, the magnetic ¯eld produced will
be oriented along the length of the coil. The greater the current, the greater the strength of the
magnetic ¯eld, all other factors being equal:
current current
magnetic field
Inductors react against changes in current because of the energy stored in this magnetic ¯eld.
When we construct a transformer from two inductor coils around a common iron core, we use this
¯eld to transfer energy from one coil to the other. However, there are simpler and more direct uses
for electromagnetic ¯elds than the applications we've seen with inductors and transformers. The
magnetic ¯eld produced by a coil of current-carrying wire can be used to exert a mechanical force
on any magnetic object, just as we can use a permanent magnet to attract magnetic objects, except
119
120 CHAPTER 5. ELECTROMECHANICAL RELAYS
that this magnet (formed by the coil) can be turned on or o® by switching the current on or o®
through the coil.
If we place a magnetic object near such a coil for the purpose of making that object move when
we energize the coil with electric current, we have what is called a solenoid. The movable magnetic
object is called an armature, and most armatures can be moved with either direct current (DC)
or alternating current (AC) energizing the coil. The polarity of the magnetic ¯eld is irrelevant for
the purpose of attracting an iron armature. Solenoids can be used to electrically open door latches,
open or shut valves, move robotic limbs, and even actuate electric switch mechanisms. However, if
a solenoid is used to actuate a set of switch contacts, we have a device so useful it deserves its own
name: the relay.
Relays are extremely useful when we have a need to control a large amount of current and/or
voltage with a small electrical signal. The relay coil which produces the magnetic ¯eld may only
consume fractions of a watt of power, while the contacts closed or opened by that magnetic ¯eld
may be able to conduct hundreds of times that amount of power to a load. In e®ect, a relay acts as
a binary (on or o®) ampli¯er.
Just as with transistors, the relay's ability to control one electrical signal with another ¯nds
application in the construction of logic functions. This topic will be covered in greater detail in
another lesson. For now, the relay's "amplifying" ability will be explored.
relay
VAC
Load
12
VDC
480
In the above schematic, the relay's coil is energized by the low-voltage (12 VDC) source, while
the single-pole, single-throw (SPST) contact interrupts the high-voltage (480 VAC) circuit. It is
quite likely that the current required to energize the relay coil will be hundreds of times less than
the current rating of the contact. Typical relay coil currents are well below 1 amp, while typical
contact ratings for industrial relays are at least 10 amps.
One relay coil/armature assembly may be used to actuate more than one set of contacts. Those
contacts may be normally-open, normally-closed, or any combination of the two. As with switches,
the "normal" state of a relay's contacts is that state when the coil is de-energized, just as you would
¯nd the relay sitting on a shelf, not connected to any circuit.
Relay contacts may be open-air pads of metal alloy, mercury tubes, or even magnetic reeds,
just as with other types of switches. The choice of contacts in a relay depends on the same factors
which dictate contact choice in other types of switches. Open-air contacts are the best for high-
current applications, but their tendency to corrode and spark may cause problems in some industrial
environments. Mercury and reed contacts are sparkless and won't corrode, but they tend to be
limited in current-carrying capacity.
5.1. RELAY CONSTRUCTION 121
Shown here are three small relays (about two inches in height, each), installed on a panel as part
of an electrical control system at a municipal water treatment plant:
The relay units shown here are called "octal-base," because they plug into matching sockets,
the electrical connections secured via eight metal pins on the relay bottom. The screw terminal
connections you see in the photograph where wires connect to the relays are actually part of the
socket assembly, into which each relay is plugged. This type of construction facilitates easy removal
and replacement of the relay(s) in the event of failure.
Aside from the ability to allow a relatively small electric signal to switch a relatively large electric
signal, relays also o®er electrical isolation between coil and contact circuits. This means that the
coil circuit and contact circuit(s) are electrically insulated from one another. One circuit may be DC
and the other AC (such as in the example circuit shown earlier), and/or they may be at completely
di®erent voltage levels, across the connections or from connections to ground.
While relays are essentially binary devices, either being completely on or completely o®, there
are operating conditions where their state may be indeterminate, just as with semiconductor logic
gates. In order for a relay to positively "pull in" the armature to actuate the contact(s), there
must be a certain minimum amount of current through the coil. This minimum amount is called
the pull-in current, and it is analogous to the minimum input voltage that a logic gate requires to
guarantee a "high" state (typically 2 Volts for TTL, 3.5 Volts for CMOS). Once the armature is
pulled closer to the coil's center, however, it takes less magnetic ¯eld °ux (less coil current) to hold
it there. Therefore, the coil current must drop below a value signi¯cantly lower than the pull-in
current before the armature "drops out" to its spring-loaded position and the contacts resume their
normal state. This current level is called the drop-out current, and it is analogous to the maximum
input voltage that a logic gate input will allow to guarantee a "low" state (typically 0.8 Volts for
TTL, 1.5 Volts for CMOS).
The hysteresis, or di®erence between pull-in and drop-out currents, results in operation that is
similar to a Schmitt trigger logic gate. Pull-in and drop-out currents (and voltages) vary widely
from relay to relay, and are speci¯ed by the manufacturer.
² REVIEW:
² A solenoid is a device that produces mechanical motion from the energization of an electro-
magnet coil. The movable portion of a solenoid is called an armature.
² A relay is a solenoid set up to actuate switch contacts when its coil is energized.
122 CHAPTER 5. ELECTROMECHANICAL RELAYS
² Pull-in current is the minimum amount of coil current needed to actuate a solenoid or relay
from its "normal" (de-energized) position.
² Drop-out current is the maximum coil current below which an energized relay will return to
its "normal" state.
5.2 Contactors
When a relay is used to switch a large amount of electrical power through its contacts, it is designated
by a special name: contactor. Contactors typically have multiple contacts, and those contacts are
usually (but not always) normally-open, so that power to the load is shut o® when the coil is de-
energized. Perhaps the most common industrial use for contactors is the control of electric motors.
motor
A
B
C
3-phase
AC power
relay
120 VAC
coil
The top three contacts switch the respective phases of the incoming 3-phase AC power, typically
at least 480 Volts for motors 1 horsepower or greater. The lowest contact is an "auxiliary" contact
which has a current rating much lower than that of the large motor power contacts, but is actuated by
the same armature as the power contacts. The auxiliary contact is often used in a relay logic circuit,
or for some other part of the motor control scheme, typically switching 120 Volt AC power instead
of the motor voltage. One contactor may have several auxiliary contacts, either normally-open or
normally-closed, if required.
The three "opposed-question-mark" shaped devices in series with each phase going to the motor
are called overload heaters. Each "heater" element is a low-resistance strip of metal intended to heat
up as the motor draws current. If the temperature of any of these heater elements reaches a critical
point (equivalent to a moderate overloading of the motor), a normally-closed switch contact (not
shown in the diagram) will spring open. This normally-closed contact is usually connected in series
with the relay coil, so that when it opens the relay will automatically de-energize, thereby shutting
o® power to the motor. We will see more of this overload protection wiring in the next chapter.
Overload heaters are intended to provide overcurrent protection for large electric motors, unlike
circuit breakers and fuses which serve the primary purpose of providing overcurrent protection for
power conductors.
Overload heater function is often misunderstood. They are not fuses; that is, it is not their
function to burn open and directly break the circuit as a fuse is designed to do. Rather, overload
heaters are designed to thermally mimic the heating characteristic of the particular electric motor
to be protected. All motors have thermal characteristics, including the amount of heat energy
5.2. CONTACTORS 123
generated by resistive dissipation (I2R), the thermal transfer characteristics of heat "conducted" to
the cooling medium through the metal frame of the motor, the physical mass and speci¯c heat of
the materials constituting the motor, etc. These characteristics are mimicked by the overload heater
on a miniature scale: when the motor heats up toward its critical temperature, so will the heater
toward its critical temperature, ideally at the same rate and approach curve. Thus, the overload
contact, in sensing heater temperature with a thermo-mechanical mechanism, will sense an analogue
of the real motor. If the overload contact trips due to excessive heater temperature, it will be an
indication that the real motor has reached its critical temperature (or, would have done so in a short
while). After tripping, the heaters are supposed to cool down at the same rate and approach curve
as the real motor, so that they indicate an accurate proportion of the motor's thermal condition,
and will not allow power to be re-applied until the motor is truly ready for start-up again.
Shown here is a contactor for a three-phase electric motor, installed on a panel as part of an
electrical control system at a municipal water treatment plant:
Three-phase, 480 volt AC power comes in to the three normally-open contacts at the top of the
contactor via screw terminals labeled "L1," "L2," and "L3" (The "L2" terminal is hidden behind
a square-shaped "snubber" circuit connected across the contactor's coil terminals). Power to the
motor exits the overload heater assembly at the bottom of this device via screw terminals labeled
"T1," "T2," and "T3."
The overload heater units themselves are black, square-shaped blocks with the label "W34,"
124 CHAPTER 5. ELECTROMECHANICAL RELAYS
indicating a particular thermal response for a certain horsepower and temperature rating of electric
motor. If an electric motor of di®ering power and/or temperature ratings were to be substituted for
the one presently in service, the overload heater units would have to be replaced with units having
a thermal response suitable for the new motor. The motor manufacturer can provide information
on the appropriate heater units to use.
A white pushbutton located between the "T1" and "T2" line heaters serves as a way to manually
re-set the normally-closed switch contact back to its normal state after having been tripped by
excessive heater temperature. Wire connections to the "overload" switch contact may be seen at
the lower-right of the photograph, near a label reading "NC" (normally-closed). On this particular
overload unit, a small "window" with the label "Tripped" indicates a tripped condition by means of
a colored °ag. In this photograph, there is no "tripped" condition, and the indicator appears clear.
As a footnote, heater elements may be used as a crude current shunt resistor for determining
whether or not a motor is drawing current when the contactor is closed. There may be times when
you're working on a motor control circuit, where the contactor is located far away from the motor
itself. How do you know if the motor is consuming power when the contactor coil is energized and
the armature has been pulled in? If the motor's windings are burnt open, you could be sending
voltage to the motor through the contactor contacts, but still have zero current, and thus no motion
from the motor shaft. If a clamp-on ammeter isn't available to measure line current, you can take
your multimeter and measure millivoltage across each heater element: if the current is zero, the
voltage across the heater will be zero (unless the heater element itself is open, in which case the
voltage across it will be large); if there is current going to the motor through that phase of the
contactor, you will read a de¯nite millivoltage across that heater:
motor
A
B
C
3-phase
AC power
relay
120 VAC
coil
V W
A COM
mV
This is an especially useful trick to use for troubleshooting 3-phase AC motors, to see if one
phase winding is burnt open or disconnected, which will result in a rapidly destructive condition
known as "single-phasing." If one of the lines carrying power to the motor is open, it will not have
any current through it (as indicated by a 0.00 mV reading across its heater), although the other two
lines will (as indicated by small amounts of voltage dropped across the respective heaters).
² REVIEW:
5.3. TIME-DELAY RELAYS 125
² A contactor is a large relay, usually used to switch current to an electric motor or other
high-power load.
² Large electric motors can be protected from overcurrent damage through the use of overload
heaters and overload contacts. If the series-connected heaters get too hot from excessive
current, the normally-closed overload contact will open, de-energizing the contactor sending
power to the motor.
5.3 Time-delay relays
Some relays are constructed with a kind of "shock absorber" mechanism attached to the armature
which prevents immediate, full motion when the coil is either energized or de-energized. This addition
gives the relay the property of time-delay actuation. Time-delay relays can be constructed to delay
armature motion on coil energization, de-energization, or both.
Time-delay relay contacts must be speci¯ed not only as either normally-open or normally-closed,
but whether the delay operates in the direction of closing or in the direction of opening. The
following is a description of the four basic types of time-delay relay contacts.
First we have the normally-open, timed-closed (NOTC) contact. This type of contact is normally
open when the coil is unpowered (de-energized). The contact is closed by the application of power
to the relay coil, but only after the coil has been continuously powered for the speci¯ed amount of
time. In other words, the direction of the contact's motion (either to close or to open) is identical
to a regular NO contact, but there is a delay in closing direction. Because the delay occurs in
the direction of coil energization, this type of contact is alternatively known as a normally-open,
on-delay:
5 sec.
Closes 5 seconds after coil energization
Opens immediately upon coil de-energization
Normally-open, timed-closed
The following is a timing diagram of this relay contact's operation:
126 CHAPTER 5. ELECTROMECHANICAL RELAYS
NOTC
5 sec.
Coil
power
Contact
status
Time
5
seconds
on
off
closed
open
Next we have the normally-open, timed-open (NOTO) contact. Like the NOTC contact, this
type of contact is normally open when the coil is unpowered (de-energized), and closed by the
application of power to the relay coil. However, unlike the NOTC contact, the timing action occurs
upon de-energization of the coil rather than upon energization. Because the delay occurs in the
direction of coil de-energization, this type of contact is alternatively known as a normally-open,
o® -delay:
5 sec.
Normally-open, timed-open
Closes immediately upon coil energization
Opens 5 seconds after coil de-energization
The following is a timing diagram of this relay contact's operation:
5.3. TIME-DELAY RELAYS 127
5 sec.
Coil
power
Contact
status
Time
5
seconds
on
off
closed
open
NOTO
Next we have the normally-closed, timed-open (NCTO) contact. This type of contact is normally
closed when the coil is unpowered (de-energized). The contact is opened with the application of power
to the relay coil, but only after the coil has been continuously powered for the speci¯ed amount of
time. In other words, the direction of the contact's motion (either to close or to open) is identical
to a regular NC contact, but there is a delay in the opening direction. Because the delay occurs in
the direction of coil energization, this type of contact is alternatively known as a normally-closed,
on-delay:
5 sec.
Normally-closed, timed-open
Opens 5 seconds after coil energization
Closes immediately upon coil de-energization
The following is a timing diagram of this relay contact's operation:
128 CHAPTER 5. ELECTROMECHANICAL RELAYS
5 sec.
Coil
power
Contact
status
Time
5
seconds
on
off
closed
open
NCTO
Finally we have the normally-closed, timed-closed (NCTC) contact. Like the NCTO contact,
this type of contact is normally closed when the coil is unpowered (de-energized), and opened by
the application of power to the relay coil. However, unlike the NCTO contact, the timing action
occurs upon de-energization of the coil rather than upon energization. Because the delay occurs in
the direction of coil de-energization, this type of contact is alternatively known as a normally-closed,
o® -delay:
5 sec.
Normally-closed, timed-closed
Opens immediately upon coil energization
Closes 5 seconds after coil de-energization
The following is a timing diagram of this relay contact's operation:
5.3. TIME-DELAY RELAYS 129
5 sec.
Coil
power
Contact
status
Time
5
seconds
on
off
closed
open
NCTC
Time-delay relays are very important for use in industrial control logic circuits. Some examples
of their use include:
² Flashing light control (time on, time o®): two time-delay relays are used in conjunction with
one another to provide a constant-frequency on/o® pulsing of contacts for sending intermittent
power to a lamp.
² Engine autostart control: Engines that are used to power emergency generators are often
equipped with "autostart" controls that allow for automatic start-up if the main electric power
fails. To properly start a large engine, certain auxiliary devices must be started ¯rst and allowed
some brief time to stabilize (fuel pumps, pre-lubrication oil pumps) before the engine's starter
motor is energized. Time-delay relays help sequence these events for proper start-up of the
engine.
² Furnace safety purge control: Before a combustion-type furnace can be safely lit, the air fan
must be run for a speci¯ed amount of time to "purge" the furnace chamber of any potentially
°ammable or explosive vapors. A time-delay relay provides the furnace control logic with this
necessary time element.
² Motor soft-start delay control: Instead of starting large electric motors by switching full power
from a dead stop condition, reduced voltage can be switched for a "softer" start and less inrush
current. After a prescribed time delay (provided by a time-delay relay), full power is applied.
² Conveyor belt sequence delay: when multiple conveyor belts are arranged to transport material,
the conveyor belts must be started in reverse sequence (the last one ¯rst and the ¯rst one last)
so that material doesn't get piled on to a stopped or slow-moving conveyor. In order to get
large belts up to full speed, some time may be needed (especially if soft-start motor controls
are used). For this reason, there is usually a time-delay circuit arranged on each conveyor
to give it adequate time to attain full belt speed before the next conveyor belt feeding it is
started.
The older, mechanical time-delay relays used pneumatic dashpots or °uid-¯lled piston/cylinder
arrangements to provide the "shock absorbing" needed to delay the motion of the armature. Newer
130 CHAPTER 5. ELECTROMECHANICAL RELAYS
designs of time-delay relays use electronic circuits with resistor-capacitor (RC) networks to generate
a time delay, then energize a normal (instantaneous) electromechanical relay coil with the electronic
circuit's output. The electronic-timer relays are more versatile than the older, mechanical models,
and less prone to failure. Many models provide advanced timer features such as "one-shot" (one
measured output pulse for every transition of the input from de-energized to energized), "recycle"
(repeated on/o® output cycles for as long as the input connection is energized) and "watchdog"
(changes state if the input signal does not repeatedly cycle on and o®).
Coil
power
Contact
status
Time
on
off
closed
open
time
"One-shot" normally-open relay contact
Coil
power
Contact
status
Time
on
off
closed
open
"Recycle" normally-open relay contact
5.3. TIME-DELAY RELAYS 131
Coil
power
Contact
status
Time
on
off
closed
open
"Watchdog" relay contact
time
The "watchdog" timer is especially useful for monitoring of computer systems. If a computer is
being used to control a critical process, it is usually recommended to have an automatic alarm to
detect computer "lockup" (an abnormal halting of program execution due to any number of causes).
An easy way to set up such a monitoring system is to have the computer regularly energize and
de-energize the coil of a watchdog timer relay (similar to the output of the "recycle" timer). If the
computer execution halts for any reason, the signal it outputs to the watchdog relay coil will stop
cycling and freeze in one or the other state. A short time thereafter, the watchdog relay will "time
out" and signal a problem.
² REVIEW:
² Time delay relays are built in these four basic modes of contact operation:
² 1: Normally-open, timed-closed. Abbreviated "NOTC", these relays open immediately upon
coil de-energization and close only if the coil is continuously energized for the time duration
period. Also called normally-open, on-delay relays.
² 2: Normally-open, timed-open. Abbreviated "NOTO", these relays close immediately upon
coil energization and open after the coil has been de-energized for the time duration period.
Also called normally-open, o® delay relays.
² 3: Normally-closed, timed-open. Abbreviated "NCTO", these relays close immediately upon
coil de-energization and open only if the coil is continuously energized for the time duration
period. Also called normally-closed, on-delay relays.
² 4: Normally-closed, timed-closed. Abbreviated "NCTC", these relays open immediately upon
coil energization and close after the coil has been de-energized for the time duration period.
Also called normally-closed, o® delay relays.
² One-shot timers provide a single contact pulse of speci¯ed duration for each coil energization
(transition from coil o® to coil on).
² Recycle timers provide a repeating sequence of on-o® contact pulses as long as the coil is
maintained in an energized state.
² Watchdog timers actuate their contacts only if the coil fails to be continuously sequenced on
and o® (energized and de-energized) at a minimum frequency.
132 CHAPTER 5. ELECTROMECHANICAL RELAYS
5.4 Protective relays
A special type of relay is one which monitors the current, voltage, frequency, or any other type of
electric power measurement either from a generating source or to a load for the purpose of triggering
a circuit breaker to open in the event of an abnormal condition. These relays are referred to in the
electrical power industry as protective relays.
The circuit breakers which are used to switch large quantities of electric power on and o® are
actually electromechanical relays, themselves. Unlike the circuit breakers found in residential and
commercial use which determine when to trip (open) by means of a bimetallic strip inside that bends
when it gets too hot from overcurrent, large industrial circuit breakers must be "told" by an external
device when to open. Such breakers have two electromagnetic coils inside: one to close the breaker
contacts and one to open them. The "trip" coil can be energized by one or more protective relays,
as well as by hand switches, connected to switch 125 Volt DC power. DC power is used because it
allows for a battery bank to supply close/trip power to the breaker control circuits in the event of
a complete (AC) power failure.
Protective relays can monitor large AC currents by means of current transformers (CT's), which
encircle the current-carrying conductors exiting a large circuit breaker, transformer, generator, or
other device. Current transformers step down the monitored current to a secondary (output) range
of 0 to 5 amps AC to power the protective relay. The current relay uses this 0-5 amp signal to power
its internal mechanism, closing a contact to switch 125 Volt DC power to the breaker's trip coil if
the monitored current becomes excessive.
Likewise, (protective) voltage relays can monitor high AC voltages by means of voltage, or
potential, transformers (PT's) which step down the monitored voltage to a secondary range of 0
to 120 Volts AC, typically. Like (protective) current relays, this voltage signal powers the internal
mechanism of the relay, closing a contact to switch 125 Volt DC power to the breaker's trip coil is
the monitored voltage becomes excessive.
There are many types of protective relays, some with highly specialized functions. Not all
monitor voltage or current, either. They all, however, share the common feature of outputting a
contact closure signal which can be used to switch power to a breaker trip coil, close coil, or operator
alarm panel. Most protective relay functions have been categorized into an ANSI standard number
code. Here are a few examples from that code list:
ANSI protective relay designation numbers
12 = Overspeed
24 = Overexcitation
25 = Syncrocheck
27 = Bus/Line undervoltage
32 = Reverse power (anti-motoring)
38 = Stator overtemp (RTD)
39 = Bearing vibration
40 = Loss of excitation
46 = Negative sequence undercurrent (phase current imbalance)
47 = Negative sequence undervoltage (phase voltage imbalance)
49 = Bearing overtemp (RTD)
50 = Instantaneous overcurrent
51 = Time overcurrent
5.5. SOLID-STATE RELAYS 133
51V = Time overcurrent -- voltage restrained
55 = Power factor
59 = Bus overvoltage
60FL = Voltage transformer fuse failure
67 = Phase/Ground directional current
79 = Autoreclose
81 = Bus over/underfrequency
² REVIEW:
² Large electric circuit breakers do not contain within themselves the necessary mechanisms to
automatically trip (open) in the event of overcurrent conditions. They must be "told" to trip
by external devices.
² Protective relays are devices built to automatically trigger the actuation coils of large electric
circuit breakers under certain conditions.
5.5 Solid-state relays
As versatile as electromechanical relays can be, they do su®er many limitations. They can be expen-
sive to build, have a limited contact cycle life, take up a lot of room, and switch slowly, compared
to modern semiconductor devices. These limitations are especially true for large power contactor
relays. To address these limitations, many relay manufacturers o®er "solid-state" relays, which use
an SCR, TRIAC, or transistor output instead of mechanical contacts to switch the controlled power.
The output device (SCR, TRIAC, or transistor) is optically-coupled to an LED light source inside
the relay. The relay is turned on by energizing this LED, usually with low-voltage DC power. This
optical isolation between input to output rivals the best that electromechanical relays can o®er.
Load
LED Opto-TRIAC
Solid-state relay
Being solid-state devices, there are no moving parts to wear out, and they are able to switch on
and o® much faster than any mechanical relay armature can move. There is no sparking between
contacts, and no problems with contact corrosion. However, solid-state relays are still too expensive
to build in very high current ratings, and so electromechanical contactors continue to dominate that
application in industry today.
One signi¯cant advantage of a solid-state SCR or TRIAC relay over an electromechanical device
is its natural tendency to open the AC circuit only at a point of zero load current. Because SCR's
and TRIAC's are thyristors, their inherent hysteresis maintains circuit continuity after the LED is
de-energized until the AC current falls below a threshold value (the holding current). In practical
terms what this means is the circuit will never be interrupted in the middle of a sine wave peak.
134 CHAPTER 5. ELECTROMECHANICAL RELAYS
Such untimely interruptions in a circuit containing substantial inductance would normally produce
large voltage spikes due to the sudden magnetic ¯eld collapse around the inductance. This will not
happen in a circuit broken by an SCR or TRIAC. This feature is called zero-crossover switching.
One disadvantage of solid state relays is their tendency to fail "shorted" on their outputs, while
electromechanical relay contacts tend to fail "open." In either case, it is possible for a relay to
fail in the other mode, but these are the most common failures. Because a "fail-open" state is
generally considered safer than a "fail-closed" state, electromechanical relays are still favored over
their solid-state counterparts in many applications.
Chapter 6
LADDER LOGIC
Contents
6.1 "Ladder" diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2 Digital logic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3 Permissive and interlock circuits . . . . . . . . . . . . . . . . . . . . . . 144
6.4 Motor control circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.5 Fail-safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.6 Programmable logic controllers . . . . . . . . . . . . . . . . . . . . . . . 154
6.7 Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.1 "Ladder" diagrams
Ladder diagrams are specialized schematics commonly used to document industrial control logic
systems. They are called "ladder" diagrams because they resemble a ladder, with two vertical rails
(supply power) and as many "rungs" (horizontal lines) as there are control circuits to represent. If
we wanted to draw a simple ladder diagram showing a lamp that is controlled by a hand switch, it
would look like this:
L1 L2
1
Switch Lamp
The "L1" and "L2" designations refer to the two poles of a 120 VAC supply, unless otherwise
noted. L1 is the "hot" conductor, and L2 is the grounded ("neutral") conductor. These designations
have nothing to do with inductors, just to make things confusing. The actual transformer or gener-
ator supplying power to this circuit is omitted for simplicity. In reality, the circuit looks something
like this:
135
136 CHAPTER 6. LADDER LOGIC
L1 L2
1
Switch Lamp
To 480 volt AC
power source (typical)
step-down "control power"
transformer
120 VAC
fuse fuse
fuse
Typically in industrial relay logic circuits, but not always, the operating voltage for the switch
contacts and relay coils will be 120 volts AC. Lower voltage AC and even DC systems are sometimes
built and documented according to "ladder" diagrams:
L1 L2
1
Switch Lamp
fuse
24 VDC
So long as the switch contacts and relay coils are all adequately rated, it really doesn't matter
what level of voltage is chosen for the system to operate with.
Note the number "1" on the wire between the switch and the lamp. In the real world, that wire
would be labeled with that number, using heat-shrink or adhesive tags, wherever it was convenient
to identify. Wires leading to the switch would be labeled "L1" and "1," respectively. Wires leading
to the lamp would be labeled "1" and "L2," respectively. These wire numbers make assembly and
maintenance very easy. Each conductor has its own unique wire number for the control system that
it's used in. Wire numbers do not change at any junction or node, even if wire size, color, or length
changes going into or out of a connection point. Of course, it is preferable to maintain consistent
wire colors, but this is not always practical. What matters is that any one, electrically continuous
point in a control circuit possesses the same wire number. Take this circuit section, for example,
with wire #25 as a single, electrically continuous point threading to many di®erent devices:
6.1. "LADDER" DIAGRAMS 137
25
25
25
25
25
25
25
25
In ladder diagrams, the load device (lamp, relay coil, solenoid coil, etc.) is almost always drawn
at the right-hand side of the rung. While it doesn't matter electrically where the relay coil is located
within the rung, it does matter which end of the ladder's power supply is grounded, for reliable
operation.
Take for instance this circuit:
L1 L2
1
Switch Lamp
120 VAC
Here, the lamp (load) is located on the right-hand side of the rung, and so is the ground connection
for the power source. This is no accident or coincidence; rather, it is a purposeful element of good
design practice. Suppose that wire #1 were to accidently come in contact with ground, the insulation
of that wire having been rubbed o® so that the bare conductor came in contact with grounded, metal
conduit. Our circuit would now function like this:
138 CHAPTER 6. LADDER LOGIC
L1 L2
1
Switch Lamp
120 VAC
accidental ground
Lamp cannot light!
Fuse will blow
if switch is
closed!
With both sides of the lamp connected to ground, the lamp will be "shorted out" and unable to
receive power to light up. If the switch were to close, there would be a short-circuit, immediately
blowing the fuse.
However, consider what would happen to the circuit with the same fault (wire #1 coming in con-
tact with ground), except this time we'll swap the positions of switch and fuse (L2 is still grounded):
L1 L2
1
Lamp Switch
120 VAC
accidental ground
Lamp is energized! Switch has no
effect!
This time the accidental grounding of wire #1 will force power to the lamp while the switch will
have no e®ect. It is much safer to have a system that blows a fuse in the event of a ground fault than
to have a system that uncontrollably energizes lamps, relays, or solenoids in the event of the same
fault. For this reason, the load(s) must always be located nearest the grounded power conductor in
6.2. DIGITAL LOGIC FUNCTIONS 139
the ladder diagram.
² REVIEW:
² Ladder diagrams (sometimes called "ladder logic") are a type of electrical notation and symbol-
ogy frequently used to illustrate how electromechanical switches and relays are interconnected.
² The two vertical lines are called "rails" and attach to opposite poles of a power supply, usually
120 volts AC. L1 designates the "hot" AC wire and L2 the "neutral" (grounded) conductor.
² Horizontal lines in a ladder diagram are called "rungs," each one representing a unique parallel
circuit branch between the poles of the power supply.
² Typically, wires in control systems are marked with numbers and/or letters for identi¯cation.
The rule is, all permanently connected (electrically common) points must bear the same label.
6.2 Digital logic functions
We can construct simply logic functions for our hypothetical lamp circuit, using multiple contacts,
and document these circuits quite easily and understandably with additional rungs to our original
"ladder." If we use standard binary notation for the status of the switches and lamp (0 for unactuated
or de-energized; 1 for actuated or energized), a truth table can be made to show how the logic works:
L1 L2
B
A
A
B
A B Output
0 0
0 1
1 0
1 1
0
1
1
1
1
Now, the lamp will come on if either contact A or contact B is actuated, because all it takes for
the lamp to be energized is to have at least one path for current from wire L1 to wire 1. What we
have is a simple OR logic function, implemented with nothing more than contacts and a lamp.
We can mimic the AND logic function by wiring the two contacts in series instead of parallel:
140 CHAPTER 6. LADDER LOGIC
L1 L2
A B
A
B
A B Output
0 0
0 1
1 0
1 1
0
1
1 2
0
0
Now, the lamp energizes only if contact A and contact B are simultaneously actuated. A path
exists for current from wire L1 to the lamp (wire 2) if and only if both switch contacts are closed.
The logical inversion, or NOT, function can be performed on a contact input simply by using a
normally-closed contact instead of a normally-open contact:
L1 L2
A
A
1
A Output
0 1
1 0
Now, the lamp energizes if the contact is not actuated, and de-energizes when the contact is
actuated.
If we take our OR function and invert each "input" through the use of normally-closed contacts,
we will end up with a NAND function. In a special branch of mathematics known as Boolean
algebra, this e®ect of gate function identity changing with the inversion of input signals is described
by DeMorgan's Theorem, a subject to be explored in more detail in a later chapter.
6.2. DIGITAL LOGIC FUNCTIONS 141
L1 L2
B
A
A
B
A B Output
0 0
0 1
1 0
1 1 0
1
1
1
1
or
A
B
The lamp will be energized if either contact is unactuated. It will go out only if both contacts
are actuated simultaneously.
Likewise, if we take our AND function and invert each "input" through the use of normally-closed
contacts, we will end up with a NOR function:
L1 L2
A B
A
B
A B Output
0 0
0 1
1 0
1 1 0
1
1
or
A
B
0
0
2
A pattern quickly reveals itself when ladder circuits are compared with their logic gate counter-
parts:
142 CHAPTER 6. LADDER LOGIC
² Parallel contacts are equivalent to an OR gate.
² Series contacts are equivalent to an AND gate.
² Normally-closed contacts are equivalent to a NOT gate (inverter).
We can build combinational logic functions by grouping contacts in series-parallel arrangements,
as well. In the following example, we have an Exclusive-OR function built from a combination of
AND, OR, and inverter (NOT) gates:
L1 L2
A B
A
B
A B Output
0 0
0 1
1 0
1 1 0
1
1
or
A
B
0
2
3
A B
2
1
The top rung (NC contact A in series with NO contact B) is the equivalent of the top NOT/AND
gate combination. The bottom rung (NO contact A in series with NC contact B) is the equivalent
of the bottom NOT/AND gate combination. The parallel connection between the two rungs at wire
number 2 forms the equivalent of the OR gate, in allowing either rung 1 or rung 2 to energize the
lamp.
To make the Exclusive-OR function, we had to use two contacts per input: one for direct input
and the other for "inverted" input. The two "A" contacts are physically actuated by the same
mechanism, as are the two "B" contacts. The common association between contacts is denoted by
the label of the contact. There is no limit to how many contacts per switch can be represented in a
ladder diagram, as each new contact on any switch or relay (either normally-open or normally-closed)
used in the diagram is simply marked with the same label.
Sometimes, multiple contacts on a single switch (or relay) are designated by a compound labels,
such as "A-1" and "A-2" instead of two "A" labels. This may be especially useful if you want to
6.2. DIGITAL LOGIC FUNCTIONS 143
speci¯cally designate which set of contacts on each switch or relay is being used for which part
of a circuit. For simplicity's sake, I'll refrain from such elaborate labeling in this lesson. If you
see a common label for multiple contacts, you know those contacts are all actuated by the same
mechanism.
If we wish to invert the output of any switch-generated logic function, we must use a relay with
a normally-closed contact. For instance, if we want to energize a load based on the inverse, or NOT,
of a normally-open contact, we could do this:
L1 L2
A
1
A Output
0 1
1 0
A CR1
CR1
CR1
0
1
2
We will call the relay, "control relay 1," or CR1. When the coil of CR1 (symbolized with the
pair of parentheses on the ¯rst rung) is energized, the contact on the second rung opens, thus de-
energizing the lamp. From switch A to the coil of CR1, the logic function is noninverted. The
normally-closed contact actuated by relay coil CR1 provides a logical inverter function to drive the
lamp opposite that of the switch's actuation status.
Applying this inversion strategy to one of our inverted-input functions created earlier, such as
the OR-to-NAND, we can invert the output with a relay to create a noninverted function:
144 CHAPTER 6. LADDER LOGIC
L1 L2
B
A
A
B
A B Output
0 0
0 1
1 0
1 1
1
or
A
B
CR1
CR1
2
0
0
0
1
From the switches to the coil of CR1, the logical function is that of a NAND gate. CR1's normally-
closed contact provides one ¯nal inversion to turn the NAND function into an AND function.
² REVIEW:
² Parallel contacts are logically equivalent to an OR gate.
² Series contacts are logically equivalent to an AND gate.
² Normally closed (N.C.) contacts are logically equivalent to a NOT gate.
² A relay must be used to invert the output of a logic gate function, while simple normally-closed
switch contacts are su±cient to represent inverted gate inputs.
6.3 Permissive and interlock circuits
A practical application of switch and relay logic is in control systems where several process conditions
have to be met before a piece of equipment is allowed to start. A good example of this is burner
control for large combustion furnaces. In order for the burners in a large furnace to be started safely,
the control system requests "permission" from several process switches, including high and low fuel
pressure, air fan °ow check, exhaust stack damper position, access door position, etc. Each process
6.3. PERMISSIVE AND INTERLOCK CIRCUITS 145
condition is called a permissive, and each permissive switch contact is wired in series, so that if any
one of them detects an unsafe condition, the circuit will be opened:
L1 L2
low fuel
pressure
high fuel
pressure
minimum
air flow open
damper CR1
green
red
CR1
CR1
Green light = conditions met: safe to start
Red light = conditions not met: unsafe to start
If all permissive conditions are met, CR1 will energize and the green lamp will be lit. In real
life, more than just a green lamp would be energized: usually a control relay or fuel valve solenoid
would be placed in that rung of the circuit to be energized when all the permissive contacts were
"good:" that is, all closed. If any one of the permissive conditions are not met, the series string of
switch contacts will be broken, CR2 will de-energize, and the red lamp will light.
Note that the high fuel pressure contact is normally-closed. This is because we want the switch
contact to open if the fuel pressure gets too high. Since the "normal" condition of any pressure
switch is when zero (low) pressure is being applied to it, and we want this switch to open with
excessive (high) pressure, we must choose a switch that is closed in its normal state.
Another practical application of relay logic is in control systems where we want to ensure two
incompatible events cannot occur at the same time. An example of this is in reversible motor control,
where two motor contactors are wired to switch polarity (or phase sequence) to an electric motor,
and we don't want the forward and reverse contactors energized simultaneously:
146 CHAPTER 6. LADDER LOGIC
motor
3-phase
AC
power
M1
M2
M1 = forward
M2 = reverse
A
B
C
1
2
3
When contactor M1 is energized, the 3 phases (A, B, and C) are connected directly to terminals
1, 2, and 3 of the motor, respectively. However, when contactor M2 is energized, phases A and B are
reversed, A going to motor terminal 2 and B going to motor terminal 1. This reversal of phase wires
results in the motor spinning the opposite direction. Let's examine the control circuit for these two
contactors:
L1 L2
forward M1 OL
reverse M2
1
2
3
Take note of the normally-closed "OL" contact, which is the thermal overload contact activated
by the "heater" elements wired in series with each phase of the AC motor. If the heaters get too
hot, the contact will change from its normal (closed) state to being open, which will prevent either
contactor from energizing.
This control system will work ¯ne, so long as no one pushes both buttons at the same time. If
someone were to do that, phases A and B would be short-circuited together by virtue of the fact
that contactor M1 sends phases A and B straight to the motor and contactor M2 reverses them;
phase A would be shorted to phase B and vice versa. Obviously, this is a bad control system design!
To prevent this occurrence from happening, we can design the circuit so that the energization
of one contactor prevents the energization of the other. This is called interlocking, and it is accom-
plished through the use of auxiliary contacts on each contactor, as such:
6.4. MOTOR CONTROL CIRCUITS 147
L1 L2
forward M1 OL
reverse M2
1
2
3
M1
M2
4
5
Now, when M1 is energized, the normally-closed auxiliary contact on the second rung will be open,
thus preventing M2 from being energized, even if the "Reverse" pushbutton is actuated. Likewise,
M1's energization is prevented when M2 is energized. Note, as well, how additional wire numbers (4
and 5) were added to re°ect the wiring changes.
It should be noted that this is not the only way to interlock contactors to prevent a short-circuit
condition. Some contactors come equipped with the option of a mechanical interlock: a lever joining
the armatures of two contactors together so that they are physically prevented from simultaneous
closure. For additional safety, electrical interlocks may still be used, and due to the simplicity of the
circuit there is no good reason not to employ them in addition to mechanical interlocks.
² REVIEW:
² Switch contacts installed in a rung of ladder logic designed to interrupt a circuit if certain
physical conditions are not met are called permissive contacts, because the system requires
permission from these inputs to activate.
² Switch contacts designed to prevent a control system from taking two incompatible actions
at once (such as powering an electric motor forward and backward simultaneously) are called
interlocks.
6.4 Motor control circuits
The interlock contacts installed in the previous section's motor control circuit work ¯ne, but the
motor will run only as long as each pushbutton switch is held down. If we wanted to keep the
motor running even after the operator takes his or her hand o® the control switch(es), we could
change the circuit in a couple of di®erent ways: we could replace the pushbutton switches with
toggle switches, or we could add some more relay logic to "latch" the control circuit with a single,
momentary actuation of either switch. Let's see how the second approach is implemented, since it
is commonly used in industry:
148 CHAPTER 6. LADDER LOGIC
L1 L2
forward M1 OL
reverse M2
1
2
3
M1
M2
4
5
M1
M2
When the "Forward" pushbutton is actuated, M1 will energize, closing the normally-open auxil-
iary contact in parallel with that switch. When the pushbutton is released, the closed M1 auxiliary
contact will maintain current to the coil of M1, thus latching the "Forward" circuit in the "on"
state. The same sort of thing will happen when the "Reverse" pushbutton is pressed. These parallel
auxiliary contacts are sometimes referred to as seal-in contacts, the word "seal" meaning essentially
the same thing as the word latch.
However, this creates a new problem: how to stop the motor! As the circuit exists right now,
the motor will run either forward or backward once the corresponding pushbutton switch is pressed,
and will continue to run as long as there is power. To stop either circuit (forward or backward), we
require some means for the operator to interrupt power to the motor contactors. We'll call this new
switch, Stop:
L1 L2
forward M1 OL
reverse M2
1
2
3
M1
M2
4
5
M1
M2
stop
6
6
6
6
6.4. MOTOR CONTROL CIRCUITS 149
Now, if either forward or reverse circuits are latched, they may be "unlatched" by momentarily
pressing the "Stop" pushbutton, which will open either forward or reverse circuit, de-energizing
the energized contactor, and returning the seal-in contact to its normal (open) state. The "Stop"
switch, having normally-closed contacts, will conduct power to either forward or reverse circuits
when released.
So far, so good. Let's consider another practical aspect of our motor control scheme before we
quit adding to it. If our hypothetical motor turned a mechanical load with a lot of momentum, such
as a large air fan, the motor might continue to coast for a substantial amount of time after the stop
button had been pressed. This could be problematic if an operator were to try to reverse the motor
direction without waiting for the fan to stop turning. If the fan was still coasting forward and the
"Reverse" pushbutton was pressed, the motor would struggle to overcome that inertia of the large
fan as it tried to begin turning in reverse, drawing excessive current and potentially reducing the life
of the motor, drive mechanisms, and fan. What we might like to have is some kind of a time-delay
function in this motor control system to prevent such a premature startup from happening.
Let's begin by adding a couple of time-delay relay coils, one in parallel with each motor contactor
coil. If we use contacts that delay returning to their normal state, these relays will provide us a
"memory" of which direction the motor was last powered to turn. What we want each time-delay
contact to do is to open the starting-switch leg of the opposite rotation circuit for several seconds,
while the fan coasts to a halt.
L1 L2
forward M1 OL
reverse M2
1
2
3
M1
M2
4
5
M1
M2
stop
6
6
6
6
TD1
TD2
TD2
TD1
7
8
If the motor has been running in the forward direction, bothM1 and TD1 will have been energized.
This being the case, the normally-closed, timed-closed contact of TD1 between wires 8 and 5 will
have immediately opened the moment TD1 was energized. When the stop button is pressed, contact
TD1 waits for the speci¯ed amount of time before returning to its normally-closed state, thus holding
the reverse pushbutton circuit open for the duration so M2 can't be energized. When TD1 times
out, the contact will close and the circuit will allow M2 to be energized, if the reverse pushbutton is
pressed. In like manner, TD2 will prevent the "Forward" pushbutton from energizing M1 until the
prescribed time delay after M2 (and TD2) have been de-energized.
The careful observer will notice that the time-interlocking functions of TD1 and TD2 render the
150 CHAPTER 6. LADDER LOGIC
M1 and M2 interlocking contacts redundant. We can get rid of auxiliary contacts M1 and M2 for
interlocks and just use TD1 and TD2's contacts, since they immediately open when their respective
relay coils are energized, thus "locking out" one contactor if the other is energized. Each time delay
relay will serve a dual purpose: preventing the other contactor from energizing while the motor
is running, and preventing the same contactor from energizing until a prescribed time after motor
shutdown. The resulting circuit has the advantage of being simpler than the previous example:
L1 L2
forward M1 OL
reverse M2
1
2
4 3
5
M1
M2
stop
6
6
6
6
TD1
TD2
TD2
TD1
² REVIEW:
² Motor contactor (or "starter") coils are typically designated by the letter "M" in ladder logic
diagrams.
² Continuous motor operation with a momentary "start" switch is possible if a normally-open
"seal-in" contact from the contactor is connected in parallel with the start switch, so that once
the contactor is energized it maintains power to itself and keeps itself "latched" on.
² Time delay relays are commonly used in large motor control circuits to prevent the motor from
being started (or reversed) until a certain amount of time has elapsed from an event.
6.5 Fail-safe design
Logic circuits, whether comprised of electromechanical relays or solid-state gates, can be built in
many di®erent ways to perform the same functions. There is usually no one "correct" way to design
a complex logic circuit, but there are usually ways that are better than others.
In control systems, safety is (or at least should be) an important design priority. If there are
multiple ways in which a digital control circuit can be designed to perform a task, and one of those
ways happens to hold certain advantages in safety over the others, then that design is the better
one to choose.
6.5. FAIL-SAFE DESIGN 151
Let's take a look at a simple system and consider how it might be implemented in relay logic.
Suppose that a large laboratory or industrial building is to be equipped with a ¯re alarm system,
activated by any one of several latching switches installed throughout the facility. The system should
work so that the alarm siren will energize if any one of the switches is actuated. At ¯rst glance it
seems as though the relay logic should be incredibly simple: just use normally-open switch contacts
and connect them all in parallel with each other:
L1 L2
switch 1 siren
switch 2
switch 3
switch 4
Essentially, this is the OR logic function implemented with four switch inputs. We could expand
this circuit to include any number of switch inputs, each new switch being added to the parallel
network, but I'll limit it to four in this example to keep things simple. At any rate, it is an elementary
system and there seems to be little possibility of trouble.
Except in the event of a wiring failure, that is. The nature of electric circuits is such that
"open" failures (open switch contacts, broken wire connections, open relay coils, blown fuses, etc.)
are statistically more likely to occur than any other type of failure. With that in mind, it makes
sense to engineer a circuit to be as tolerant as possible to such a failure. Let's suppose that a wire
connection for Switch #2 were to fail open:
152 CHAPTER 6. LADDER LOGIC
L1 L2
switch 1 siren
switch 2
switch 3
switch 4
open wire connection!
If this failure were to occur, the result would be that Switch #2 would no longer energize the siren
if actuated. This, obviously, is not good in a ¯re alarm system. Unless the system were regularly
tested (a good idea anyway), no one would know there was a problem until someone tried to use
that switch in an emergency.
What if the system were re-engineered so as to sound the alarm in the event of an open failure?
That way, a failure in the wiring would result in a false alarm, a scenario much more preferable than
that of having a switch silently fail and not function when needed. In order to achieve this design
goal, we would have to re-wire the switches so that an open contact sounded the alarm, rather than
a closed contact. That being the case, the switches will have to be normally-closed and in series
with each other, powering a relay coil which then activates a normally-closed contact for the siren:
L1 L2
switch 1
switch 2
switch 3
switch 4
CR1
CR1 siren
When all switches are unactuated (the regular operating state of this system), relay CR1 will
be energized, thus keeping contact CR1 open, preventing the siren from being powered. However,
if any of the switches are actuated, relay CR1 will de-energize, closing contact CR1 and sounding
the alarm. Also, if there is a break in the wiring anywhere in the top rung of the circuit, the alarm
will sound. When it is discovered that the alarm is false, the workers in the facility will know that
something failed in the alarm system and that it needs to be repaired.
Granted, the circuit is more complex than it was before the addition of the control relay, and
the system could still fail in the "silent" mode with a broken connection in the bottom rung, but
it's still a safer design than the original circuit, and thus preferable from the standpoint of safety.
6.5. FAIL-SAFE DESIGN 153
This design of circuit is referred to as fail-safe, due to its intended design to default to the safest
mode in the event of a common failure such as a broken connection in the switch wiring. Fail-safe
design always starts with an assumption as to the most likely kind of wiring or component failure,
and then tries to con¯gure things so that such a failure will cause the circuit to act in the safest
way, the "safest way" being determined by the physical characteristics of the process.
Take for example an electrically-actuated (solenoid) valve for turning on cooling water to a
machine. Energizing the solenoid coil will move an armature which then either opens or closes the
valve mechanism, depending on what kind of valve we specify. A spring will return the valve to its
"normal" position when the solenoid is de-energized. We already know that an open failure in the
wiring or solenoid coil is more likely than a short or any other type of failure, so we should design
this system to be in its safest mode with the solenoid de-energized.
If it's cooling water we're controlling with this valve, chances are it is safer to have the cooling
water turn on in the event of a failure than to shut o®, the consequences of a machine running
without coolant usually being severe. This means we should specify a valve that turns on (opens
up) when de-energized and turns o® (closes down) when energized. This may seem "backwards" to
have the valve set up this way, but it will make for a safer system in the end.
One interesting application of fail-safe design is in the power generation and distribution industry,
where large circuit breakers need to be opened and closed by electrical control signals from protective
relays. If a 50/51 relay (instantaneous and time overcurrent) is going to command a circuit breaker
to trip (open) in the event of excessive current, should we design it so that the relay closes a switch
contact to send a "trip" signal to the breaker, or opens a switch contact to interrupt a regularly
"on" signal to initiate a breaker trip? We know that an open connection will be the most likely to
occur, but what is the safest state of the system: breaker open or breaker closed?
At ¯rst, it would seem that it would be safer to have a large circuit breaker trip (open up and
shut o® power) in the event of an open fault in the protective relay control circuit, just like we
had the ¯re alarm system default to an alarm state with any switch or wiring failure. However,
things are not so simple in the world of high power. To have a large circuit breaker indiscriminately
trip open is no small matter, especially when customers are depending on the continued supply
of electric power to supply hospitals, telecommunications systems, water treatment systems, and
other important infrastructures. For this reason, power system engineers have generally agreed to
design protective relay circuits to output a closed contact signal (power applied) to open large circuit
breakers, meaning that any open failure in the control wiring will go unnoticed, simply leaving the
breaker in the status quo position.
Is this an ideal situation? Of course not. If a protective relay detects an overcurrent condition
while the control wiring is failed open, it will not be able to trip open the circuit breaker. Like the
¯rst ¯re alarm system design, the "silent" failure will be evident only when the system is needed.
However, to engineer the control circuitry the other way { so that any open failure would immediately
shut the circuit breaker o®, potentially blacking out large potions of the power grid { really isn't a
better alternative.
An entire book could be written on the principles and practices of good fail-safe system design.
At least here, you know a couple of the fundamentals: that wiring tends to fail open more often than
shorted, and that an electrical control system's (open) failure mode should be such that it indicates
and/or actuates the real-life process in the safest alternative mode. These fundamental principles
extend to non-electrical systems as well: identify the most common mode of failure, then engineer
the system so that the probable failure mode places the system in the safest condition.
154 CHAPTER 6. LADDER LOGIC
² REVIEW:
² The goal of fail-safe design is to make a control system as tolerant as possible to likely wiring
or component failures.
² The most common type of wiring and component failure is an "open" circuit, or broken connec-
tion. Therefore, a fail-safe system should be designed to default to its safest mode of operation
in the case of an open circuit.
6.6 Programmable logic controllers
Before the advent of solid-state logic circuits, logical control systems were designed and built ex-
clusively around electromechanical relays. Relays are far from obsolete in modern design, but have
been replaced in many of their former roles as logic-level control devices, relegated most often to
those applications demanding high current and/or high voltage switching.
Systems and processes requiring "on/o®" control abound in modern commerce and industry,
but such control systems are rarely built from either electromechanical relays or discrete logic gates.
Instead, digital computers ¯ll the need, which may be programmed to do a variety of logical functions.
In the late 1960's an American company named Bedford Associates released a computing device
they called the MODICON. As an acronym, it meant Modular Digital Controller, and later became
the name of a company division devoted to the design, manufacture, and sale of these special-purpose
control computers. Other engineering ¯rms developed their own versions of this device, and it
eventually came to be known in non-proprietary terms as a PLC, or Programmable Logic Controller.
The purpose of a PLC was to directly replace electromechanical relays as logic elements, substituting
instead a solid-state digital computer with a stored program, able to emulate the interconnection of
many relays to perform certain logical tasks.
A PLC has many "input" terminals, through which it interprets "high" and "low" logical states
from sensors and switches. It also has many output terminals, through which it outputs "high"
and "low" signals to power lights, solenoids, contactors, small motors, and other devices lending
themselves to on/o® control. In an e®ort to make PLCs easy to program, their programming
language was designed to resemble ladder logic diagrams. Thus, an industrial electrician or electrical
engineer accustomed to reading ladder logic schematics would feel comfortable programming a PLC
to perform the same control functions.
PLCs are industrial computers, and as such their input and output signals are typically 120 volts
AC, just like the electromechanical control relays they were designed to replace. Although some
PLCs have the ability to input and output low-level DC voltage signals of the magnitude used in
logic gate circuits, this is the exception and not the rule.
Signal connection and programming standards vary somewhat between di®erent models of PLC,
but they are similar enough to allow a "generic" introduction to PLC programming here. The
following illustration shows a simple PLC, as it might appear from a front view. Two screw terminals
provide connection to 120 volts AC for powering the PLC's internal circuitry, labeled L1 and L2. Six
screw terminals on the left-hand side provide connection to input devices, each terminal representing
a di®erent input "channel" with its own "X" label. The lower-left screw terminal is a "Common"
connection, which is generally connected to L2 (neutral) of the 120 VAC power source.
6.6. PROGRAMMABLE LOGIC CONTROLLERS 155
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
Inside the PLC housing, connected between each input terminal and the Common terminal, is an
opto-isolator device (Light-Emitting Diode) that provides an electrically isolated "high" logic signal
to the computer's circuitry (a photo-transistor interprets the LED's light) when there is 120 VAC
power applied between the respective input terminal and the Common terminal. An indicating LED
on the front panel of the PLC gives visual indication of an "energized" input:
PLC
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
Common port Source
L1 L2
X2
X3
X4
X5
X6
V W
A COM
120 V
Input X1 energized
Output signals are generated by the PLC's computer circuitry activating a switching device
(transistor, TRIAC, or even an electromechanical relay), connecting the "Source" terminal to any
of the "Y-" labeled output terminals. The "Source" terminal, correspondingly, is usually connected
to the L1 side of the 120 VAC power source. As with each input, an indicating LED on the front
panel of the PLC gives visual indication of an "energized" output:
156 CHAPTER 6. LADDER LOGIC
PLC
L1 L2
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X2
X3
X4
X5
X6
V W
A COM
120 V
X1
Output Y1 energized
In this way, the PLC is able to interface with real-world devices such as switches and solenoids.
The actual logic of the control system is established inside the PLC by means of a computer pro-
gram. This program dictates which output gets energized under which input conditions. Although
the program itself appears to be a ladder logic diagram, with switch and relay symbols, there are
no actual switch contacts or relay coils operating inside the PLC to create the logical relationships
between input and output. These are imaginary contacts and coils, if you will. The program is
entered and viewed via a personal computer connected to the PLC's programming port.
Consider the following circuit and PLC program:
6.6. PROGRAMMABLE LOGIC CONTROLLERS 157
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
Personal
computer
Programming
X1 Y1 cable
display
When the pushbutton switch is unactuated (unpressed), no power is sent to the X1 input of
the PLC. Following the program, which shows a normally-open X1 contact in series with a Y1 coil,
no "power" will be sent to the Y1 coil. Thus, the PLC's Y1 output remains de-energized, and the
indicator lamp connected to it remains dark.
If the pushbutton switch is pressed, however, power will be sent to the PLC's X1 input. Any
and all X1 contacts appearing in the program will assume the actuated (non-normal) state, as
though they were relay contacts actuated by the energizing of a relay coil named "X1". In this case,
energizing the X1 input will cause the normally-open X1 contact will "close," sending "power" to
the Y1 coil. When the Y1 coil of the program "energizes," the real Y1 output will become energized,
lighting up the lamp connected to it:
158 CHAPTER 6. LADDER LOGIC
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
Personal
computer
Programming
X1 Y1 cable
display
switch actuated
lamp
lights!
contact and coil symbols
turn color, indicating "power"
conducted through "circuit"
It must be understood that the X1 contact, Y1 coil, connecting wires, and "power" appearing
in the personal computer's display are all virtual. They do not exist as real electrical components.
They exist as commands in a computer program { a piece of software only { that just happens to
resemble a real relay schematic diagram.
Equally important to understand is that the personal computer used to display and edit the
PLC's program is not necessary for the PLC's continued operation. Once a program has been
loaded to the PLC from the personal computer, the personal computer may be unplugged from
the PLC, and the PLC will continue to follow the programmed commands. I include the personal
computer display in these illustrations for your sake only, in aiding to understand the relationship
between real-life conditions (switch closure and lamp status) and the program's status ("power"
through virtual contacts and virtual coils).
The true power and versatility of a PLC is revealed when we want to alter the behavior of a
control system. Since the PLC is a programmable device, we can alter its behavior by changing the
commands we give it, without having to recon¯gure the electrical components connected to it. For
example, suppose we wanted to make this switch-and-lamp circuit function in an inverted fashion:
push the button to make the lamp turn o®, and release it to make it turn on. The "hardware"
solution would require that a normally-closed pushbutton switch be substituted for the normally-
6.6. PROGRAMMABLE LOGIC CONTROLLERS 159
open switch currently in place. The "software" solution is much easier: just alter the program so
that contact X1 is normally-closed rather than normally-open.
In the following illustration, we have the altered system shown in the state where the pushbutton
is unactuated (not being pressed):
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
Personal
computer
Programming
X1 Y1 cable
display
lamp
lights!
colored components show
"power" conducted through
the "circuit" with contact X1
in its "normal" status
In this next illustration, the switch is shown actuated (pressed):
160 CHAPTER 6. LADDER LOGIC
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
Personal
computer
Programming
X1 Y1 cable
display
switch actuated
lamp is
dark
un-colored components
show no "continuity" in
the "circuit"
One of the advantages of implementing logical control in software rather than in hardware is that
input signals can be re-used as many times in the program as is necessary. For example, take the
following circuit and program, designed to energize the lamp if at least two of the three pushbutton
switches are simultaneously actuated:
6.6. PROGRAMMABLE LOGIC CONTROLLERS 161
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
X2 X3
X1 X3
To build an equivalent circuit using electromechanical relays, three relays with two normally-
open contacts each would have to be used, to provide two contacts per input switch. Using a PLC,
however, we can program as many contacts as we wish for each "X" input without adding additional
hardware, since each input and each output is nothing more than a single bit in the PLC's digital
memory (either 0 or 1), and can be recalled as many times as necessary.
Furthermore, since each output in the PLC is nothing more than a bit in its memory as well, we
can assign contacts in a PLC program "actuated" by an output (Y) status. Take for instance this
next system, a motor start-stop control circuit:
162 CHAPTER 6. LADDER LOGIC
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
Y1
Motor
start
Motor
stop
M1
Motor
contactor
The pushbutton switch connected to input X1 serves as the "Start" switch, while the switch
connected to input X2 serves as the "Stop." Another contact in the program, named Y1, uses the
output coil status as a seal-in contact, directly, so that the motor contactor will continue to be
energized after the "Start" pushbutton switch is released. You can see the normally-closed contact
X2 appear in a colored block, showing that it is in a closed ("electrically conducting") state.
If we were to press the "Start" button, input X1 would energize, thus "closing" the X1 contact
in the program, sending "power" to the Y1 "coil," energizing the Y1 output and applying 120 volt
AC power to the real motor contactor coil. The parallel Y1 contact will also "close," thus latching
the "circuit" in an energized state:
6.6. PROGRAMMABLE LOGIC CONTROLLERS 163
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
Y1
Motor
start
Motor
stop
M1
Motor
contactor
(actuated)
(energized)
Now, if we release the "Start" pushbutton, the normally-open X1 "contact" will return to its
"open" state, but the motor will continue to run because the Y1 seal-in "contact" continues to
provide "continuity" to "power" coil Y1, thus keeping the Y1 output energized:
164 CHAPTER 6. LADDER LOGIC
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
Y1
Motor
start
Motor
stop
M1
Motor
contactor
(energized)
(released)
To stop the motor, we must momentarily press the "Stop" pushbutton, which will energize the
X2 input and "open" the normally-closed "contact," breaking continuity to the Y1 "coil:"
6.6. PROGRAMMABLE LOGIC CONTROLLERS 165
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
Y1
Motor
start
Motor
stop
M1
Motor
contactor
(actuated)
When the "Stop" pushbutton is released, input X2 will de-energize, returning "contact" X2 to
its normal, "closed" state. The motor, however, will not start again until the "Start" pushbutton is
actuated, because the "seal-in" of Y1 has been lost:
166 CHAPTER 6. LADDER LOGIC
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
Y1
Motor
start
Motor
stop
M1
Motor
contactor
(released)
An important point to make here is that fail-safe design is just as important in PLC-controlled
systems as it is in electromechanical relay-controlled systems. One should always consider the
e®ects of failed (open) wiring on the device or devices being controlled. In this motor control circuit
example, we have a problem: if the input wiring for X2 (the "Stop" switch) were to fail open, there
would be no way to stop the motor!
The solution to this problem is a reversal of logic between the X2 "contact" inside the PLC
program and the actual "Stop" pushbutton switch:
6.6. PROGRAMMABLE LOGIC CONTROLLERS 167
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1 X2 Y1
Y1
Motor
start
Motor
stop
M1
Motor
contactor
When the normally-closed "Stop" pushbutton switch is unactuated (not pressed), the PLC's
X2 input will be energized, thus "closing" the X2 "contact" inside the program. This allows the
motor to be started when input X1 is energized, and allows it to continue to run when the "Start"
pushbutton is no longer pressed. When the "Stop" pushbutton is actuated, input X2 will de-energize,
thus "opening" the X2 "contact" inside the PLC program and shutting o® the motor. So, we see
there is no operational di®erence between this new design and the previous design.
However, if the input wiring on input X2 were to fail open, X2 input would de-energize in the
same manner as when the "Stop" pushbutton is pressed. The result, then, for a wiring failure on the
X2 input is that the motor will immediately shut o®. This is a safer design than the one previously
shown, where a "Stop" switch wiring failure would have resulted in an inability to turn o® the motor.
In addition to input (X) and output (Y) program elements, PLCs provide "internal" coils and
contacts with no intrinsic connection to the outside world. These are used much the same as "control
relays" (CR1, CR2, etc.) are used in standard relay circuits: to provide logic signal inversion when
necessary.
To demonstrate how one of these "internal" relays might be used, consider the following example
circuit and program, designed to emulate the function of a three-input NAND gate. Since PLC
program elements are typically designed by single letters, I will call the internal control relay "C1"
168 CHAPTER 6. LADDER LOGIC
rather than "CR1" as would be customary in a relay control circuit:
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1
Y1
X2 X3 C1
C1
lamp
lights!
In this circuit, the lamp will remain lit so long as any of the pushbuttons remain unactuated
(unpressed). To make the lamp turn o®, we will have to actuate (press) all three switches, like this:
6.6. PROGRAMMABLE LOGIC CONTROLLERS 169
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
X1
Y1
X2 X3 C1
C1
All three switches actuated
lamp is
dark
This section on programmable logic controllers illustrates just a small sample of their capabilities.
As computers, PLCs can perform timing functions (for the equivalent of time-delay relays), drum
sequencing, and other advanced functions with far greater accuracy and reliability than what is
possible using electromechanical logic devices. Most PLCs have the capacity for far more than six
inputs and six outputs. The following photograph shows several input and output modules of a
single Allen-Bradley PLC.
170 CHAPTER 6. LADDER LOGIC
With each module having sixteen "points" of either input or output, this PLC has the ability
to monitor and control dozens of devices. Fit into a control cabinet, a PLC takes up little room,
especially considering the equivalent space that would be needed by electromechanical relays to
perform the same functions:
One advantage of PLCs that simply cannot be duplicated by electromechanical relays is remote
monitoring and control via digital computer networks. Because a PLC is nothing more than a
special-purpose digital computer, it has the ability to communicate with other computers rather
easily. The following photograph shows a personal computer displaying a graphic image of a real
liquid-level process (a pumping, or "lift," station for a municipal wastewater treatment system)
controlled by a PLC. The actual pumping station is located miles away from the personal computer
display:
6.7. CONTRIBUTORS 171
6.7 Contributors
Contributors to this chapter are listed in chronological order of their contributions, from most recent
to ¯rst. See Appendix 2 (Contributor List) for dates and contact information.
Roger Hollingsworth (May 2003): Suggested a way to make the PLC motor control circuit
fail-safe.
172 CHAPTER 6. LADDER LOGIC
Chapter 7
BOOLEAN ALGEBRA
Contents
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.2 Boolean arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.3 Boolean algebraic identities . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.4 Boolean algebraic properties . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.5 Boolean rules for simpli¯cation . . . . . . . . . . . . . . . . . . . . . . . 184
7.6 Circuit simpli¯cation examples . . . . . . . . . . . . . . . . . . . . . . . 187
7.7 The Exclusive-OR function . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.8 DeMorgan's Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.9 Converting truth tables into Boolean expressions . . . . . . . . . . . . 200
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
Rules of addition for Boolean quantities
"Gee Toto, I don't think we're in Kansas anymore!"
Dorothy, in The Wizard of Oz
7.1 Introduction
Mathematical rules are based on the de¯ning limits we place on the particular numerical quantities
dealt with. When we say that 1 + 1 = 2 or 3 + 4 = 7, we are implying the use of integer quantities:
the same types of numbers we all learned to count in elementary education. What most people
173
174 CHAPTER 7. BOOLEAN ALGEBRA
assume to be self-evident rules of arithmetic { valid at all times and for all purposes { actually
depend on what we de¯ne a number to be.
For instance, when calculating quantities in AC circuits, we ¯nd that the "real" number quantities
which served us so well in DC circuit analysis are inadequate for the task of representing AC
quantities. We know that voltages add when connected in series, but we also know that it is possible
to connect a 3-volt AC source in series with a 4-volt AC source and end up with 5 volts total voltage
(3 + 4 = 5)! Does this mean the inviolable and self-evident rules of arithmetic have been violated?
No, it just means that the rules of "real" numbers do not apply to the kinds of quantities encountered
in AC circuits, where every variable has both a magnitude and a phase. Consequently, we must use
a di®erent kind of numerical quantity, or object, for AC circuits (complex numbers, rather than real
numbers), and along with this di®erent system of numbers comes a di®erent set of rules telling us
how they relate to one another.
An expression such as "3 + 4 = 5" is nonsense within the scope and de¯nition of real numbers,
but it ¯ts nicely within the scope and de¯nition of complex numbers (think of a right triangle with
opposite and adjacent sides of 3 and 4, with a hypotenuse of 5). Because complex numbers are two-
dimensional, they are able to "add" with one another trigonometrically as single-dimension "real"
numbers cannot.
Logic is much like mathematics in this respect: the so-called "Laws" of logic depend on how we
de¯ne what a proposition is. The Greek philosopher Aristotle founded a system of logic based on
only two types of propositions: true and false. His bivalent (two-mode) de¯nition of truth led to the
four foundational laws of logic: the Law of Identity (A is A); the Law of Non-contradiction (A is not
non-A); the Law of the Excluded Middle (either A or non-A); and the Law of Rational Inference.
These so-called Laws function within the scope of logic where a proposition is limited to one of two
possible values, but may not apply in cases where propositions can hold values other than "true" or
"false." In fact, much work has been done and continues to be done on "multivalued," or fuzzy logic,
where propositions may be true or false to a limited degree. In such a system of logic, "Laws" such as
the Law of the Excluded Middle simply do not apply, because they are founded on the assumption of
bivalence. Likewise, many premises which would violate the Law of Non-contradiction in Aristotelian
logic have validity in "fuzzy" logic. Again, the de¯ning limits of propositional values determine the
Laws describing their functions and relations.
The English mathematician George Boole (1815-1864) sought to give symbolic form to Aristotle's
system of logic. Boole wrote a treatise on the subject in 1854, titled An Investigation of the Laws
of Thought, on Which Are Founded the Mathematical Theories of Logic and Probabilities, which
codi¯ed several rules of relationship between mathematical quantities limited to one of two possible
values: true or false, 1 or 0. His mathematical system became known as Boolean algebra.
All arithmetic operations performed with Boolean quantities have but one of two possible out-
comes: either 1 or 0. There is no such thing as "2" or "-1" or "1/2" in the Boolean world. It
is a world in which all other possibilities are invalid by ¯at. As one might guess, this is not the
kind of math you want to use when balancing a checkbook or calculating current through a resis-
tor. However, Claude Shannon of MIT fame recognized how Boolean algebra could be applied to
on-and-o® circuits, where all signals are characterized as either "high" (1) or "low" (0). His 1938
thesis, titled A Symbolic Analysis of Relay and Switching Circuits, put Boole's theoretical work to
use in a way Boole never could have imagined, giving us a powerful mathematical tool for designing
and analyzing digital circuits.
In this chapter, you will ¯nd a lot of similarities between Boolean algebra and "normal" algebra,
the kind of algebra involving so-called real numbers. Just bear in mind that the system of numbers
7.2. BOOLEAN ARITHMETIC 175
de¯ning Boolean algebra is severely limited in terms of scope, and that there can only be one of two
possible values for any Boolean variable: 1 or 0. Consequently, the "Laws" of Boolean algebra often
di®er from the "Laws" of real-number algebra, making possible such statements as 1 + 1 = 1, which
would normally be considered absurd. Once you comprehend the premise of all quantities in Boolean
algebra being limited to the two possibilities of 1 and 0, and the general philosophical principle of
Laws depending on quantitative de¯nitions, the "nonsense" of Boolean algebra disappears.
It should be clearly understood that Boolean numbers are not the same as binary numbers.
Whereas Boolean numbers represent an entirely di®erent system of mathematics from real numbers,
binary is nothing more than an alternative notation for real numbers. The two are often confused
because both Boolean math and binary notation use the same two ciphers: 1 and 0. The di®erence
is that Boolean quantities are restricted to a single bit (either 1 or 0), whereas binary numbers may
be composed of many bits adding up in place-weighted form to a value of any ¯nite size. The binary
number 100112 ("nineteen") has no more place in the Boolean world than the decimal number 210
("two") or the octal number 328 ("twenty-six").
7.2 Boolean arithmetic
Let us begin our exploration of Boolean algebra by adding numbers together:
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
The ¯rst three sums make perfect sense to anyone familiar with elementary addition. The last
sum, though, is quite possibly responsible for more confusion than any other single statement in
digital electronics, because it seems to run contrary to the basic principles of mathematics. Well,
it does contradict principles of addition for real numbers, but not for Boolean numbers. Remember
that in the world of Boolean algebra, there are only two possible values for any quantity and for
any arithmetic operation: 1 or 0. There is no such thing as "2" within the scope of Boolean values.
Since the sum "1 + 1" certainly isn't 0, it must be 1 by process of elimination.
It does not matter how many or few terms we add together, either. Consider the following sums:
0 + 1 + 1 = 1
0 + 1 + 1 + 1 = 1
1 + 0 + 1 + 1 + 1 = 1
1 + 1 + 1 = 1
Take a close look at the two-term sums in the ¯rst set of equations. Does that pattern look
familiar to you? It should! It is the same pattern of 1's and 0's as seen in the truth table for an OR
gate. In other words, Boolean addition corresponds to the logical function of an "OR" gate, as well
as to parallel switch contacts:
176 CHAPTER 7. BOOLEAN ALGEBRA
0 + 0 = 0
0
0
0
0 0
0
0
0
0 + 1 = 1
1
1
1
1
0
0
1
1 1
1
1 + 0 = 1
1
1 1
1
1 + 1 = 1
1
1
There is no such thing as subtraction in the realm of Boolean mathematics. Subtraction implies
the existence of negative numbers: 5 - 3 is the same thing as 5 + (-3), and in Boolean algebra negative
quantities are forbidden. There is no such thing as division in Boolean mathematics, either, since
division is really nothing more than compounded subtraction, in the same way that multiplication
is compounded addition.
Multiplication is valid in Boolean algebra, and thankfully it is the same as in real-number algebra:
anything multiplied by 0 is 0, and anything multiplied by 1 remains unchanged:
0 ´ 0 = 0
0 ´ 1 = 0
1 ´ 0 = 0
1 ´ 1 = 1
This set of equations should also look familiar to you: it is the same pattern found in the truth
table for an AND gate. In other words, Boolean multiplication corresponds to the logical function
7.2. BOOLEAN ARITHMETIC 177
of an "AND" gate, as well as to series switch contacts:
0 ´ 0 = 0
0
0
0
0 0 0
0
0
0 0
0 ´ 1 = 0
1
1
0
0
0 0
1
1
1 ´ 0 = 0
1
1
1
1
1 ´ 1 = 1
1 1
Like "normal" algebra, Boolean algebra uses alphabetical letters to denote variables. Unlike
"normal" algebra, though, Boolean variables are always CAPITAL letters, never lower-case. Because
they are allowed to possess only one of two possible values, either 1 or 0, each and every variable
has a complement: the opposite of its value. For example, if variable "A" has a value of 0, then
the complement of A has a value of 1. Boolean notation uses a bar above the variable character to
denote complementation, like this:
If: A=0
Then: A=1
If:
Then:
A=1
A=0
In written form, the complement of "A" denoted as "A-not" or "A-bar". Sometimes a "prime"
symbol is used to represent complementation. For example, A' would be the complement of A, much
the same as using a prime symbol to denote di®erentiation in calculus rather than the fractional
notation d/dt. Usually, though, the "bar" symbol ¯nds more widespread use than the "prime"
symbol, for reasons that will become more apparent later in this chapter.
Boolean complementation ¯nds equivalency in the form of the NOT gate, or a normally-closed
switch or relay contact:
178 CHAPTER 7. BOOLEAN ALGEBRA
1
If:
Then: A=1
A=0
0
A A 0 1
A A
1
If:
Then:
A=1
A=0
0
A A 1 0
A A
The basic de¯nition of Boolean quantities has led to the simple rules of addition and multipli-
cation, and has excluded both subtraction and division as valid arithmetic operations. We have
a symbology for denoting Boolean variables, and their complements. In the next section we will
proceed to develop Boolean identities.
² REVIEW:
² Boolean addition is equivalent to the OR logic function, as well as parallel switch contacts.
² Boolean multiplication is equivalent to the AND logic function, as well as series switch con-
tacts.
² Boolean complementation is equivalent to the NOT logic function, as well as normally-closed
relay contacts.
7.3 Boolean algebraic identities
In mathematics, an identity is a statement true for all possible values of its variable or variables.
The algebraic identity of x + 0 = x tells us that anything (x) added to zero equals the original
"anything," no matter what value that "anything" (x) may be. Like ordinary algebra, Boolean
algebra has its own unique identities based on the bivalent states of Boolean variables.
The ¯rst Boolean identity is that the sum of anything and zero is the same as the original
"anything." This identity is no di®erent from its real-number algebraic equivalent:
0
0
0
A + 0 = A
A
A A
No matter what the value of A, the output will always be the same: when A=1, the output will
also be 1; when A=0, the output will also be 0.
7.3. BOOLEAN ALGEBRAIC IDENTITIES 179
The next identity is most de¯nitely di®erent from any seen in normal algebra. Here we discover
that the sum of anything and one is one:
A
A
A + 1 = 1
1
1
1
1
No matter what the value of A, the sum of A and 1 will always be 1. In a sense, the "1" signal
overrides the e®ect of A on the logic circuit, leaving the output ¯xed at a logic level of 1.
Next, we examine the e®ect of adding A and A together, which is the same as connecting both
inputs of an OR gate to each other and activating them with the same signal:
A
A
1
A + A = A
A
A
In real-number algebra, the sum of two identical variables is twice the original variable's value
(x + x = 2x), but remember that there is no concept of "2" in the world of Boolean math, only 1
and 0, so we cannot say that A + A = 2A. Thus, when we add a Boolean quantity to itself, the sum
is equal to the original quantity: 0 + 0 = 0, and 1 + 1 = 1.
Introducing the uniquely Boolean concept of complementation into an additive identity, we ¯nd
an interesting e®ect. Since there must be one "1" value between any variable and its complement,
and since the sum of any Boolean quantity and 1 is 1, the sum of a variable and its complement
must be 1:
A
A
1
A
A + A = 1
A 1
A
Just as there are four Boolean additive identities (A+0, A+1, A+A, and A+A'), so there are
also four multiplicative identities: Ax0, Ax1, AxA, and AxA'. Of these, the ¯rst two are no di®erent
from their equivalent expressions in regular algebra:
180 CHAPTER 7. BOOLEAN ALGEBRA
A
A
0A = 0
0
0
0 0
A
A
1A = A
1
A
1 A
The third multiplicative identity expresses the result of a Boolean quantity multiplied by itself.
In normal algebra, the product of a variable and itself is the square of that variable (3 x 3 = 32
= 9). However, the concept of "square" implies a quantity of 2, which has no meaning in Boolean
algebra, so we cannot say that A x A = A2. Instead, we ¯nd that the product of a Boolean quantity
and itself is the original quantity, since 0 x 0 = 0 and 1 x 1 = 1:
A
A
A
A
AA = A
A
The fourth multiplicative identity has no equivalent in regular algebra because it uses the com-
plement of a variable, a concept unique to Boolean mathematics. Since there must be one "0" value
between any variable and its complement, and since the product of any Boolean quantity and 0 is
0, the product of a variable and its complement must be 0:
A
A A
AA = 0
0
A
A
0
To summarize, then, we have four basic Boolean identities for addition and four for multiplication:
A + 0 = A
A + 1 = 1
A + A = A
A + A = 1
0A = 0
1A = A
AA = A
AA = 0
Additive Multiplicative
Basic Boolean algebraic identities
Another identity having to do with complementation is that of the double complement: a variable
inverted twice. Complementing a variable twice (or any even number of times) results in the original
7.4. BOOLEAN ALGEBRAIC PROPERTIES 181
Boolean value. This is analogous to negating (multiplying by -1) in real-number algebra: an even
number of negations cancel to leave the original value:
A
A A
A = A
A
A
(same)
A
CR1
CR1 CR2
CR2
A
A
(same)
7.4 Boolean algebraic properties
Another type of mathematical identity, called a "property" or a "law," describes how di®ering
variables relate to each other in a system of numbers. One of these properties is known as the com-
mutative property, and it applies equally to addition and multiplication. In essence, the commutative
property tells us we can reverse the order of variables that are either added together or multiplied
together without changing the truth of the expression:
Commutative property of addition
A + B = B + A
A
B
A
B
(same)
A
B
A
B
(same)
182 CHAPTER 7. BOOLEAN ALGEBRA
A
B
A
B
(same)
A B
B A
(same)
Commutative property of multiplication
AB = BA
Along with the commutative properties of addition and multiplication, we have the associative
property, again applying equally well to addition and multiplication. This property tells us we can
associate groups of added or multiplied variables together with parentheses without altering the
truth of the equations.
A
B
A
B
Associative property of addition
A + (B + C) = (A + B) + C
C
A
B
C
(same)
C
A
B
C
(same)
7.4. BOOLEAN ALGEBRAIC PROPERTIES 183
A
B
A
B
C
A
B
C
(same)
C
Associative property of multiplication
A(BC) = (AB)C
A B
C
(same)
Lastly, we have the distributive property, illustrating how to expand a Boolean expression formed
by the product of a sum, and in reverse shows us how terms may be factored out of Boolean sums-
of-products:
A
B
A B
C
A
B
C
(same)
C
A B
C
(same)
Distributive property
A(B + C) = AB + AC
A A
To summarize, here are the three basic properties: commutative, associative, and distributive.
184 CHAPTER 7. BOOLEAN ALGEBRA
Additive Multiplicative
Basic Boolean algebraic properties
A + (B + C) = (A + B) + C A(BC) = (AB)C
A + B = B + A AB = BA
A(B + C) = AB + AC
7.5 Boolean rules for simpli¯cation
Boolean algebra ¯nds its most practical use in the simpli¯cation of logic circuits. If we translate a
logic circuit's function into symbolic (Boolean) form, and apply certain algebraic rules to the resulting
equation to reduce the number of terms and/or arithmetic operations, the simpli¯ed equation may
be translated back into circuit form for a logic circuit performing the same function with fewer
components. If equivalent function may be achieved with fewer components, the result will be
increased reliability and decreased cost of manufacture.
To this end, there are several rules of Boolean algebra presented in this section for use in reducing
expressions to their simplest forms. The identities and properties already reviewed in this chapter
are very useful in Boolean simpli¯cation, and for the most part bear similarity to many identities and
properties of "normal" algebra. However, the rules shown in this section are all unique to Boolean
mathematics.
A
B
(same) A
A B
(same)
A + AB = A
A
AB
A + AB
A
A
A
This rule may be proven symbolically by factoring an "A" out of the two terms, then applying
the rules of A + 1 = 1 and 1A = A to achieve the ¯nal result:
7.5. BOOLEAN RULES FOR SIMPLIFICATION 185
A + AB
A(1 + B)
Applying identity A + 1 = 1
A(1)
Applying identity 1A = A
A
Factoring A out of both terms
Please note how the rule A + 1 = 1 was used to reduce the (B + 1) term to 1. When a rule
like "A + 1 = 1" is expressed using the letter "A", it doesn't mean it only applies to expressions
containing "A". What the "A" stands for in a rule like A + 1 = 1 is any Boolean variable or
collection of variables. This is perhaps the most di±cult concept for new students to master in
Boolean simpli¯cation: applying standardized identities, properties, and rules to expressions not in
standard form.
For instance, the Boolean expression ABC + 1 also reduces to 1 by means of the "A + 1 = 1"
identity. In this case, we recognize that the "A" term in the identity's standard form can represent
the entire "ABC" term in the original expression.
The next rule looks similar to the ¯rst on shown in this section, but is actually quite di®erent
and requires a more clever proof:
B (same)
A
A
B
(same)
A
AB
A + AB
A
A
A + AB = A + B
A
A + B
B
186 CHAPTER 7. BOOLEAN ALGEBRA
A + AB
Applying the previous rule to expand A term
A + AB = A
A + AB + AB
A + B(A + A)
Applying identity A + A = 1
A + B(1)
Applying identity 1A = A
A + B
Factoring B out of 2nd and 3rd terms
Note how the last rule (A + AB = A) is used to "un-simplify" the ¯rst "A" term in the expression,
changing the "A" into an "A + AB". While this may seem like a backward step, it certainly helped
to reduce the expression to something simpler! Sometimes in mathematics we must take "backward"
steps to achieve the most elegant solution. Knowing when to take such a step and when not to is
part of the art-form of algebra, just as a victory in a game of chess almost always requires calculated
sacri¯ces.
Another rule involves the simpli¯cation of a product-of-sums expression:
A
A
B
(same)
A
(A + B)(A + C) = A + BC
B
A
C
A+B
A+C
A
B
C
BC
(A+B)(A+C)
A + BC
(same)
A
C
B C
And, the corresponding proof:
7.6. CIRCUIT SIMPLIFICATION EXAMPLES 187
(A + B)(A + C)
Distributing terms
AA + AC + AB + BC
Applying identity AA = A
A + AC + AB + BC
Applying rule A + AB = A
to the A + AC term
A + AB + BC
Applying rule A + AB = A
to the A + AB term
A + BC
To summarize, here are the three new rules of Boolean simpli¯cation expounded in this section:
Useful Boolean rules for simplification
A + AB = A
A + AB = A + B
(A + B)(A + C) = A + BC
7.6 Circuit simpli¯cation examples
Let's begin with a semiconductor gate circuit in need of simpli¯cation. The "A," "B," and "C" input
signals are assumed to be provided from switches, sensors, or perhaps other gate circuits. Where
these signals originate is of no concern in the task of gate reduction.
A
B
C
Q
Our ¯rst step in simpli¯cation must be to write a Boolean expression for this circuit. This task
is easily performed step by step if we start by writing sub-expressions at the output of each gate,
corresponding to the respective input signals for each gate. Remember that OR gates are equivalent
to Boolean addition, while AND gates are equivalent to Boolean multiplication. For example, I'll
write sub-expressions at the outputs of the ¯rst three gates:
188 CHAPTER 7. BOOLEAN ALGEBRA
A
B
C
Q
AB
B+C
BC
. . . then another sub-expression for the next gate:
A
B
C
Q
AB
B+C
BC
BC(B+C)
Finally, the output ("Q") is seen to be equal to the expression AB + BC(B + C):
A
B
C
AB
B+C
BC
BC(B+C)
Q = AB + BC(B+C)
Now that we have a Boolean expression to work with, we need to apply the rules of Boolean
algebra to reduce the expression to its simplest form (simplest de¯ned as requiring the fewest gates
to implement):
7.6. CIRCUIT SIMPLIFICATION EXAMPLES 189
Distributing terms
Applying identity AA = A
AB + BBC + BCC
AB + BC + BC
Applying identity A + A = A
to 2nd and 3rd terms
to 2nd and 3rd terms
AB + BC
Factoring B out of terms
B(A + C)
AB + BC(B + C)
The ¯nal expression, B(A + C), is much simpler than the original, yet performs the same function.
If you would like to verify this, you may generate a truth table for both expressions and determine
Q's status (the circuits' output) for all eight logic-state combinations of A, B, and C, for both
circuits. The two truth tables should be identical.
Now, we must generate a schematic diagram from this Boolean expression. To do this, evaluate
the expression, following proper mathematical order of operations (multiplication before addition,
operations inside parentheses before anything else), and draw gates for each step. Remember again
that OR gates are equivalent to Boolean addition, while AND gates are equivalent to Boolean
multiplication. In this case, we would begin with the sub-expression "A + C", which is an OR gate:
A
C
A+C
The next step in evaluating the expression "B(A + C)" is to multiply (AND gate) the signal B
by the output of the previous gate (A + C):
A
C
A+C
B
Q = B(A+C)
Obviously, this circuit is much simpler than the original, having only two logic gates instead of
¯ve. Such component reduction results in higher operating speed (less delay time from input signal
transition to output signal transition), less power consumption, less cost, and greater reliability.
Electromechanical relay circuits, typically being slower, consuming more electrical power to op-
erate, costing more, and having a shorter average life than their semiconductor counterparts, bene¯t
dramatically from Boolean simpli¯cation. Let's consider an example circuit:
190 CHAPTER 7. BOOLEAN ALGEBRA
L1 L2
A Q
B A
C
A C
As before, our ¯rst step in reducing this circuit to its simplest form must be to develop a Boolean
expression from the schematic. The easiest way I've found to do this is to follow the same steps I'd
normally follow to reduce a series-parallel resistor network to a single, total resistance. For example,
examine the following resistor network with its resistors arranged in the same connection pattern as
the relay contacts in the former circuit, and corresponding total resistance formula:
R1
R2 R3
R4
R5 R6
Rtotal
Rtotal = R1 // [(R3//R4) -- R2] // (R5 -- R6)
Remember that parallel contacts are equivalent to Boolean addition, while series contacts are
equivalent to Boolean multiplication. Write a Boolean expression for this relay contact circuit,
following the same order of precedence that you would follow in reducing a series-parallel resistor
network to a total resistance. It may be helpful to write a Boolean sub-expression to the left of each
ladder "rung," to help organize your expression-writing:
7.6. CIRCUIT SIMPLIFICATION EXAMPLES 191
L1 L2
A Q
B A
C
A C
Q = A + B(A+C) + AC
A
B(A+C)
AC
Now that we have a Boolean expression to work with, we need to apply the rules of Boolean
algebra to reduce the expression to its simplest form (simplest de¯ned as requiring the fewest relay
contacts to implement):
Distributing terms
A + B(A + C) + AC
A + AB + BC + AC
Applying rule A + AB = A
to 1st and 2nd terms
A + BC + AC
Applying rule A + AB = A
to 1st and 3rd terms
A + BC
The more mathematically inclined should be able to see that the two steps employing the rule
"A + AB = A" may be combined into a single step, the rule being expandable to: "A + AB + AC
+ AD + . . . = A"
Distributing terms
A + B(A + C) + AC
A + AB + BC + AC
A + BC
Applying (expanded) rule A + AB = A
to 1st, 2nd, and 4th terms
As you can see, the reduced circuit is much simpler than the original, yet performs the same
logical function:
192 CHAPTER 7. BOOLEAN ALGEBRA
L1 L2
A Q
B C
A A + BC
BC
² REVIEW:
² To convert a gate circuit to a Boolean expression, label each gate output with a Boolean sub-
expression corresponding to the gates' input signals, until a ¯nal expression is reached at the
last gate.
² To convert a Boolean expression to a gate circuit, evaluate the expression using standard
order of operations: multiplication before addition, and operations within parentheses before
anything else.
² To convert a ladder logic circuit to a Boolean expression, label each rung with a Boolean sub-
expression corresponding to the contacts' input signals, until a ¯nal expression is reached at
the last coil or light. To determine proper order of evaluation, treat the contacts as though they
were resistors, and as if you were determining total resistance of the series-parallel network
formed by them. In other words, look for contacts that are either directly in series or directly
in parallel with each other ¯rst, then "collapse" them into equivalent Boolean sub-expressions
before proceeding to other contacts.
² To convert a Boolean expression to a ladder logic circuit, evaluate the expression using standard
order of operations: multiplication before addition, and operations within parentheses before
anything else.
7.7 The Exclusive-OR function
One element conspicuously missing from the set of Boolean operations is that of Exclusive-OR.
Whereas the OR function is equivalent to Boolean addition, the AND function to Boolean multi-
plication, and the NOT function (inverter) to Boolean complementation, there is no direct Boolean
equivalent for Exclusive-OR. This hasn't stopped people from developing a symbol to represent it,
though:
A
B
A Å B
This symbol is seldom used in Boolean expressions because the identities, laws, and rules of
simpli¯cation involving addition, multiplication, and complementation do not apply to it. However,
there is a way to represent the Exclusive-OR function in terms of OR and AND, as has been shown
in previous chapters: AB' + A'B
7.8. DEMORGAN'S THEOREMS 193
A
B
A Å B
A
B
. . . is equivalent to . . .
AB
AB
AB + AB
A Å B = AB + AB
As a Boolean equivalency, this rule may be helpful in simplifying some Boolean expressions. Any
expression following the AB' + A'B form (two AND gates and an OR gate) may be replaced by a
single Exclusive-OR gate.
7.8 DeMorgan's Theorems
A mathematician named DeMorgan developed a pair of important rules regarding group comple-
mentation in Boolean algebra. By group complementation, I'm referring to the complement of a
group of terms, represented by a long bar over more than one variable.
You should recall from the chapter on logic gates that inverting all inputs to a gate reverses that
gate's essential function from AND to OR, or vice versa, and also inverts the output. So, an OR
gate with all inputs inverted (a Negative-OR gate) behaves the same as a NAND gate, and an AND
gate with all inputs inverted (a Negative-AND gate) behaves the same as a NOR gate. DeMorgan's
theorems state the same equivalence in "backward" form: that inverting the output of any gate
results in the same function as the opposite type of gate (AND vs. OR) with inverted inputs:
194 CHAPTER 7. BOOLEAN ALGEBRA
A
B
AB
AB
. . . is equivalent to . . .
A
B
A
B
A + B
AB = A + B
A long bar extending over the term AB acts as a grouping symbol, and as such is entirely di®erent
from the product of A and B independently inverted. In other words, (AB)' is not equal to A'B'.
Because the "prime" symbol (') cannot be stretched over two variables like a bar can, we are forced
to use parentheses to make it apply to the whole term AB in the previous sentence. A bar, however,
acts as its own grouping symbol when stretched over more than one variable. This has profound
impact on how Boolean expressions are evaluated and reduced, as we shall see.
DeMorgan's theorem may be thought of in terms of breaking a long bar symbol. When a long
bar is broken, the operation directly underneath the break changes from addition to multiplication,
or vice versa, and the broken bar pieces remain over the individual variables. To illustrate:
AB
break!
A + B
A + B
break!
AB
NAND to Negative-OR NOR to Negative-AND
DeMorgan’s Theorems
When multiple "layers" of bars exist in an expression, you may only break one bar at a time,
and it is generally easier to begin simpli¯cation by breaking the longest (uppermost) bar ¯rst. To
illustrate, let's take the expression (A + (BC)')' and reduce it using DeMorgan's Theorems:
B
C
BC
A
A
A + BC
7.8. DEMORGAN'S THEOREMS 195
Following the advice of breaking the longest (uppermost) bar ¯rst, I'll begin by breaking the bar
covering the entire expression as a ¯rst step:
A + BC
Breaking longest bar
A BC
Applying identity A = A
to BC
ABC
(addition changes to multiplication)
As a result, the original circuit is reduced to a three-input AND gate with the A input inverted:
A
B
C
A
ABC
You should never break more than one bar in a single step, as illustrated here:
A + BC
Applying identity A = A
Breaking long bar between A and B;
Breaking both bars between B and C
A B + C
Incorrect step!
to B and C
Incorrect answer: AB + C
As tempting as it may be to conserve steps and break more than one bar at a time, it often leads
to an incorrect result, so don't do it!
It is possible to properly reduce this expression by breaking the short bar ¯rst, rather than the
long bar ¯rst:
196 CHAPTER 7. BOOLEAN ALGEBRA
A + BC
Breaking shortest bar
(multiplication changes to addition)
A + (B + C)
Applying associative property
to remove parentheses
A + B + C
Breaking long bar in two places,
between 1st and 2nd terms;
between 2nd and 3rd terms
A B C
Applying identity A = A
ABC
to B and C
The end result is the same, but more steps are required compared to using the ¯rst method,
where the longest bar was broken ¯rst. Note how in the third step we broke the long bar in two
places. This is a legitimate mathematical operation, and not the same as breaking two bars in one
step! The prohibition against breaking more than one bar in one step is not a prohibition against
breaking a bar in more than one place. Breaking in more than one place in a single step is okay;
breaking more than one bar in a single step is not.
You might be wondering why parentheses were placed around the sub-expression B' + C', con-
sidering the fact that I just removed them in the next step. I did this to emphasize an important but
easily neglected aspect of DeMorgan's theorem. Since a long bar functions as a grouping symbol,
the variables formerly grouped by a broken bar must remain grouped lest proper precedence (order
of operation) be lost. In this example, it really wouldn't matter if I forgot to put parentheses in
after breaking the short bar, but in other cases it might. Consider this example, starting with a
di®erent expression:
AB + CD
Breaking bar in middle
(AB)(CD)
Breaking both bars in middle
(A + B)(C + D)
Notice the grouping maintained
with parentheses
Correct answer:
7.8. DEMORGAN'S THEOREMS 197
AB + CD
Breaking bar in middle
Breaking both bars in middle
AB CD
Incorrect answer: A + BC + D
Parentheses omitted
As you can see, maintaining the grouping implied by the complementation bars for this expression
is crucial to obtaining the correct answer.
Let's apply the principles of DeMorgan's theorems to the simpli¯cation of a gate circuit:
Q
A
B
C
As always, our ¯rst step in simplifying this circuit must be to generate an equivalent Boolean
expression. We can do this by placing a sub-expression label at the output of each gate, as the
inputs become known. Here's the ¯rst step in this process:
Q
A
B
C BC
B
Next, we can label the outputs of the ¯rst NOR gate and the NAND gate. When dealing with
inverted-output gates, I ¯nd it easier to write an expression for the gate's output without the ¯nal
inversion, with an arrow pointing to just before the inversion bubble. Then, at the wire leading out
of the gate (after the bubble), I write the full, complemented expression. This helps ensure I don't
forget a complementing bar in the sub-expression, by forcing myself to split the expression-writing
task into two steps:
198 CHAPTER 7. BOOLEAN ALGEBRA
Q
A
B
C BC
B
A
A+BC
A+BC
AB
AB
Finally, we write an expression (or pair of expressions) for the last NOR gate:
A
B
C BC
B
A
A+BC
A+BC
AB
AB A+BC + AB
Q = A+BC + AB
Now, we reduce this expression using the identities, properties, rules, and theorems (DeMorgan's)
of Boolean algebra:
7.8. DEMORGAN'S THEOREMS 199
Applying identity A = A
A + BC + AB
Breaking longest bar
(A + BC) (AB)
wherever double bars of
equal length are found
(A + BC)(AB)
Distributive property
AAB + BCAB
Applying identity AA = A
to left term; applying identity
AA = 0 to B and B in right
term
AB + 0
Applying identity A + 0 = A
AB
The equivalent gate circuit for this much-simpli¯ed expression is as follows:
A
B
Q = AB
² REVIEW
² DeMorgan's Theorems describe the equivalence between gates with inverted inputs and gates
with inverted outputs. Simply put, a NAND gate is equivalent to a Negative-OR gate, and a
NOR gate is equivalent to a Negative-AND gate.
² When "breaking" a complementation bar in a Boolean expression, the operation directly un-
derneath the break (addition or multiplication) reverses, and the broken bar pieces remain
over the respective terms.
² It is often easier to approach a problem by breaking the longest (uppermost) bar before break-
ing any bars under it. You must never attempt to break two bars in one step!
² Complementation bars function as grouping symbols. Therefore, when a bar is broken, the
terms underneath it must remain grouped. Parentheses may be placed around these grouped
terms as a help to avoid changing precedence.
200 CHAPTER 7. BOOLEAN ALGEBRA
7.9 Converting truth tables into Boolean expressions
In designing digital circuits, the designer often begins with a truth table describing what the circuit
should do. The design task is largely to determine what type of circuit will perform the function
described in the truth table. While some people seem to have a natural ability to look at a truth
table and immediately envision the necessary logic gate or relay logic circuitry for the task, there
are procedural techniques available for the rest of us. Here, Boolean algebra proves its utility in a
most dramatic way.
To illustrate this procedural method, we should begin with a realistic design problem. Suppose
we were given the task of designing a °ame detection circuit for a toxic waste incinerator. The intense
heat of the ¯re is intended to neutralize the toxicity of the waste introduced into the incinerator.
Such combustion-based techniques are commonly used to neutralize medical waste, which may be
infected with deadly viruses or bacteria:
flame
Toxic waste
inlet
Fuel
Exhaust inlet
Toxic waste incinerator
So long as a °ame is maintained in the incinerator, it is safe to inject waste into it to be
neutralized. If the °ame were to be extinguished, however, it would be unsafe to continue to inject
waste into the combustion chamber, as it would exit the exhaust un-neutralized, and pose a health
threat to anyone in close proximity to the exhaust. What we need in this system is a sure way of
detecting the presence of a °ame, and permitting waste to be injected only if a °ame is "proven" by
the °ame detection system.
Several di®erent °ame-detection technologies exist: optical (detection of light), thermal (detec-
tion of high temperature), and electrical conduction (detection of ionized particles in the °ame
path), each one with its unique advantages and disadvantages. Suppose that due to the high degree
of hazard involved with potentially passing un-neutralized waste out the exhaust of this incinerator,
it is decided that the °ame detection system be made redundant (multiple sensors), so that fail-
ure of a single sensor does not lead to an emission of toxins out the exhaust. Each sensor comes
equipped with a normally-open contact (open if no °ame, closed if °ame detected) which we will
use to activate the inputs of a logic system:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 201
flame
Toxic waste
inlet
Fuel
Exhaust inlet
Toxic waste incinerator
sensor sensor sensor
Logic system
(shuts off waste valve
if no flame detected)
Waste shutoff
valve
A B C
Our task, now, is to design the circuitry of the logic system to open the waste valve if and only if
there is good °ame proven by the sensors. First, though, we must decide what the logical behavior of
this control system should be. Do we want the valve to be opened if only one out of the three sensors
detects °ame? Probably not, because this would defeat the purpose of having multiple sensors. If
any one of the sensors were to fail in such a way as to falsely indicate the presence of °ame when
there was none, a logic system based on the principle of "any one out of three sensors showing °ame"
would give the same output that a single-sensor system would with the same failure. A far better
solution would be to design the system so that the valve is commanded to open if any only if all
three sensors detect a good °ame. This way, any single, failed sensor falsely showing °ame could
not keep the valve in the open position; rather, it would require all three sensors to be failed in the
same manner { a highly improbable scenario { for this dangerous condition to occur.
Thus, our truth table would look like this:
202 CHAPTER 7. BOOLEAN ALGEBRA
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
It does not require much insight to realize that this functionality could be generated with a
three-input AND gate: the output of the circuit will be "high" if and only if input A AND input B
AND input C are all "high:"
flame
Toxic waste
inlet
Fuel
Exhaust inlet
Toxic waste incinerator
sensor sensor sensor
Waste shutoff
valve
A B C
Vdd
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 203
If using relay circuitry, we could create this AND function by wiring three relay contacts in series,
or simply by wiring the three sensor contacts in series, so that the only way electrical power could
be sent to open the waste valve is if all three sensors indicate °ame:
flame
Toxic waste
inlet
Fuel
Exhaust inlet
Toxic waste incinerator
sensor sensor sensor
Waste shutoff
valve
A B C
L1
While this design strategy maximizes safety, it makes the system very susceptible to sensor
failures of the opposite kind. Suppose that one of the three sensors were to fail in such a way that
it indicated no °ame when there really was a good °ame in the incinerator's combustion chamber.
That single failure would shut o® the waste valve unnecessarily, resulting in lost production time
and wasted fuel (feeding a ¯re that wasn't being used to incinerate waste).
It would be nice to have a logic system that allowed for this kind of failure without shutting the
system down unnecessarily, yet still provide sensor redundancy so as to maintain safety in the event
that any single sensor failed "high" (showing °ame at all times, whether or not there was one to
detect). A strategy that would meet both needs would be a "two out of three" sensor logic, whereby
the waste valve is opened if at least two out of the three sensors show good °ame. The truth table
for such a system would look like this:
204 CHAPTER 7. BOOLEAN ALGEBRA
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
1
1
1
Here, it is not necessarily obvious what kind of logic circuit would satisfy the truth table. How-
ever, a simple method for designing such a circuit is found in a standard form of Boolean expression
called the Sum-Of-Products, or SOP, form. As you might suspect, a Sum-Of-Products Boolean
expression is literally a set of Boolean terms added (summed) together, each term being a multi-
plicative (product) combination of Boolean variables. An example of an SOP expression would be
something like this: ABC + BC + DF, the sum of products "ABC," "BC," and "DF."
Sum-Of-Products expressions are easy to generate from truth tables. All we have to do is examine
the truth table for any rows where the output is "high" (1), and write a Boolean product term that
would equal a value of 1 given those input conditions. For instance, in the fourth row down in the
truth table for our two-out-of-three logic system, where A=0, B=1, and C=1, the product term
would be A'BC, since that term would have a value of 1 if and only if A=0, B=1, and C=1:
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
1
1
1 ABC = 1
Three other rows of the truth table have an output value of 1, so those rows also need Boolean
product expressions to represent them:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 205
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
1
1
1 ABC = 1
ABC = 1
ABC = 1
ABC = 1
Finally, we join these four Boolean product expressions together by addition, to create a single
Boolean expression describing the truth table as a whole:
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
1
1
1 ABC = 1
ABC = 1
ABC = 1
ABC = 1
Output = ABC + ABC + ABC + ABC
Now that we have a Boolean Sum-Of-Products expression for the truth table's function, we can
easily design a logic gate or relay logic circuit based on that expression:
206 CHAPTER 7. BOOLEAN ALGEBRA
Output = ABC + ABC + ABC + ABC
A B C
ABC
ABC
ABC
ABC
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 207
Output = ABC + ABC + ABC + ABC
A
B
C
ABC
ABC
ABC
L1 L2
CR1
CR2
CR3
Output
ABC
CR1 CR2 CR3
CR1 CR2 CR3
CR1 CR2 CR3
CR1 CR2 CR3
Unfortunately, both of these circuits are quite complex, and could bene¯t from simpli¯cation.
Using Boolean algebra techniques, the expression may be signi¯cantly simpli¯ed:
208 CHAPTER 7. BOOLEAN ALGEBRA
ABC + ABC + ABC + ABC
Factoring BC out of 1st and 4th terms
BC(A + A) + ABC + ABC
Applying identity A + A = 1
BC(1) + ABC + ABC
Applying identity 1A = A
BC + ABC + ABC
Factoring B out of 1st and 3rd terms
B(C + AC) + ABC
Applying rule A + AB = A + B to
the C + AC term
B(C + A) + ABC
Distributing terms
BC + AB + ABC
Factoring A out of 2nd and 3rd terms
BC + A(B + BC)
Applying rule A + AB = A + B to
the B + BC term
BC + A(B + C)
Distributing terms
BC + AB + AC
or
AB + BC + AC
Simplified result
As a result of the simpli¯cation, we can now build much simpler logic circuits performing the
same function, in either gate or relay form:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 209
A B C
Output = AB + BC + AC
AB
BC
AC
A
B
C
L1 L2
CR1
CR2
CR3
CR1 CR2 Output
CR2 CR3
CR1 CR3
AB
BC
AC
Output = AB + BC + AC
Either one of these circuits will adequately perform the task of operating the incinerator waste
valve based on a °ame veri¯cation from two out of the three °ame sensors. At minimum, this is
what we need to have a safe incinerator system. We can, however, extend the functionality of the
system by adding to it logic circuitry designed to detect if any one of the sensors does not agree
210 CHAPTER 7. BOOLEAN ALGEBRA
with the other two.
If all three sensors are operating properly, they should detect °ame with equal accuracy. Thus,
they should either all register "low" (000: no °ame) or all register "high" (111: good °ame). Any
other output combination (001, 010, 011, 100, 101, or 110) constitutes a disagreement between
sensors, and may therefore serve as an indicator of a potential sensor failure. If we added circuitry
to detect any one of the six "sensor disagreement" conditions, we could use the output of that
circuitry to activate an alarm. Whoever is monitoring the incinerator would then exercise judgment
in either continuing to operate with a possible failed sensor (inputs: 011, 101, or 110), or shut the
incinerator down to be absolutely safe. Also, if the incinerator is shut down (no °ame), and one or
more of the sensors still indicates °ame (001, 010, 011, 100, 101, or 110) while the other(s) indicate(s)
no °ame, it will be known that a de¯nite sensor problem exists.
The ¯rst step in designing this "sensor disagreement" detection circuit is to write a truth table
describing its behavior. Since we already have a truth table describing the output of the "good
°ame" logic circuit, we can simply add another output column to the table to represent the second
circuit, and make a table representing the entire logic system:
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
1
1
1
Good
flame
0
0
1
1
1
1
1
1
Output
Sensor
disagreement
Output = 0
(sensors agree)
Output = 1
(sensors disagree)
While it is possible to generate a Sum-Of-Products expression for this new truth table column,
it would require six terms, of three variables each! Such a Boolean expression would require many
steps to simplify, with a large potential for making algebraic errors:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 211
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
1
1
1
Good
flame
0
0
1
1
1
1
1
1
Output
Sensor
disagreement
Output = 0
(sensors agree)
Output = 1
(sensors disagree)
ABC
ABC
ABC
ABC
ABC
ABC
Output = ABC + ABC + ABC + ABC + ABC + ABC
An alternative to generating a Sum-Of-Products expression to account for all the "high" (1)
output conditions in the truth table is to generate a Product-Of-Sums, or POS, expression, to
account for all the "low" (0) output conditions instead. Being that there are much fewer instances
of a "low" output in the last truth table column, the resulting Product-Of-Sums expression should
contain fewer terms. As its name suggests, a Product-Of-Sums expression is a set of added terms
(sums), which are multiplied (product) together. An example of a POS expression would be (A +
B)(C + D), the product of the sums "A + B" and "C + D".
To begin, we identify which rows in the last truth table column have "low" (0) outputs, and
write a Boolean sum term that would equal 0 for that row's input conditions. For instance, in the
¯rst row of the truth table, where A=0, B=0, and C=0, the sum term would be (A + B + C), since
that term would have a value of 0 if and only if A=0, B=0, and C=0:
212 CHAPTER 7. BOOLEAN ALGEBRA
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
1
1
1
Good
flame
0
0
1
1
1
1
1
1
Output
Sensor
disagreement
Output = 0
(sensors agree)
Output = 1
(sensors disagree)
(A + B + C)
Only one other row in the last truth table column has a "low" (0) output, so all we need is one
more sum term to complete our Product-Of-Sums expression. This last sum term represents a 0
output for an input condition of A=1, B=1 and C=1. Therefore, the term must be written as (A' +
B'+ C'), because only the sum of the complemented input variables would equal 0 for that condition
only:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 213
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
1
1
1
Good
flame
0
0
1
1
1
1
1
1
Output
Sensor
disagreement
Output = 0
(sensors agree)
Output = 1
(sensors disagree)
(A + B + C)
(A + B + C)
The completed Product-Of-Sums expression, of course, is the multiplicative combination of these
two sum terms:
A B C Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1
0
0
0
0
sensor
inputs
Output = 1
(open valve)
Output = 0
(close valve)
1
1
1
Good
flame
0
0
1
1
1
1
1
1
Output
Sensor
disagreement
Output = 0
(sensors agree)
Output = 1
(sensors disagree)
(A + B + C)
(A + B + C)
Output = (A + B + C)(A + B + C)
214 CHAPTER 7. BOOLEAN ALGEBRA
Whereas a Sum-Of-Products expression could be implemented in the form of a set of AND
gates with their outputs connecting to a single OR gate, a Product-Of-Sums expression can be
implemented as a set of OR gates feeding into a single AND gate:
A B C
Output = (A + B + C)(A + B + C)
(A + B + C)
(A + B + C)
Correspondingly, whereas a Sum-Of-Products expression could be implemented as a parallel
collection of series-connected relay contacts, a Product-Of-Sums expression can be implemented as
a series collection of parallel-connected relay contacts:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 215
A
B
C
L1 L2
CR1
CR2
CR3
Output
CR2 CR2
CR3
Output = (A + B + C)(A + B + C)
CR3
CR1 CR1
(A + B + C) (A + B + C)
The previous two circuits represent di®erent versions of the "sensor disagreement" logic circuit
only, not the "good °ame" detection circuit(s). The entire logic system would be the combination
of both "good °ame" and "sensor disagreement" circuits, shown on the same diagram.
Implemented in a Programmable Logic Controller (PLC), the entire logic system might resemble
something like this:
216 CHAPTER 7. BOOLEAN ALGEBRA
PLC
X1
X2
X3
X4
X5
X6
L1 L2 Y1
Y2
Y3
Y4
Y5
Y6
Programming
port
Common Source
L1 L2
Personal
computer
Programming
X1 Y1 cable
display
Sensor
A
Sensor
Sensor
B
C
Waste valve
solenoid
Sensor
disagreement
alarm lamp
X2
X1
X2 X3
X3
X1
X2
X3
X1
X2
X3
Y2
As you can see, both the Sum-Of-Products and Products-Of-Sums standard Boolean forms are
powerful tools when applied to truth tables. They allow us to derive a Boolean expression { and
ultimately, an actual logic circuit { from nothing but a truth table, which is a written speci¯cation for
what we want a logic circuit to do. To be able to go from a written speci¯cation to an actual circuit
using simple, deterministic procedures means that it is possible to automate the design process for
a digital circuit. In other words, a computer could be programmed to design a custom logic circuit
from a truth table speci¯cation! The steps to take from a truth table to the ¯nal circuit are so
unambiguous and direct that it requires little, if any, creativity or other original thought to execute
them.
² REVIEW:
7.9. CONVERTING TRUTH TABLES INTO BOOLEAN EXPRESSIONS 217
² Sum-Of-Products, or SOP, Boolean expressions may be generated from truth tables quite
easily, by determining which rows of the table have an output of 1, writing one product term
for each row, and ¯nally summing all the product terms. This creates a Boolean expression
representing the truth table as a whole.
² Sum-Of-Products expressions lend themselves well to implementation as a set of AND gates
(products) feeding into a single OR gate (sum).
² Product-Of-Sums, or POS, Boolean expressions may also be generated from truth tables quite
easily, by determining which rows of the table have an output of 0, writing one sum term
for each row, and ¯nally multiplying all the sum terms. This creates a Boolean expression
representing the truth table as a whole.
² Product-Of-Sums expressions lend themselves well to implementation as a set of OR gates
(sums) feeding into a single AND gate (product).
218 CHAPTER 7. BOOLEAN ALGEBRA
Chapter 8
KARNAUGH MAPPING
Contents
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.2 Venn diagrams and sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3 Boolean Relationships on Venn Diagrams . . . . . . . . . . . . . . . . . 223
8.4 Making a Venn diagram look like a Karnaugh map . . . . . . . . . . . 228
8.5 Karnaugh maps, truth tables, and Boolean expressions . . . . . . . . 231
8.6 Logic simpli¯cation with Karnaugh maps . . . . . . . . . . . . . . . . . 238
8.7 Larger 4-variable Karnaugh maps . . . . . . . . . . . . . . . . . . . . . 245
8.8 Minterm vs maxterm solution . . . . . . . . . . . . . . . . . . . . . . . . 249
8.9 § (sum) and ¦ (product) notation . . . . . . . . . . . . . . . . . . . . . 261
8.10 Don't care cells in the Karnaugh map . . . . . . . . . . . . . . . . . . . 263
8.11 Larger 5 & 6-variable Karnaugh maps . . . . . . . . . . . . . . . . . . . 266
Original author: Dennis Crunkilton
A
C B C BC BC
A
0
1
B A 00 01 1110
BC
8.1 Introduction
Why learn about Karnaugh maps? The Karnaugh map, like Boolean algebra, is a simpli¯cation tool
applicable to digital logic. See the "Toxic waste incinerator" in the Boolean algebra chapter for an
example of Boolean simpli¯cation of digital logic. The Karnaugh Map will simplify logic faster and
more easily in most cases.
219
220 CHAPTER 8. KARNAUGH MAPPING
Boolean simpli¯cation is actually faster than the Karnaugh map for a task involving two or fewer
Boolean variables. It is still quite usable at three variables, but a bit slower. At four input variables,
Boolean algebra becomes tedious. Karnaugh maps are both faster and easier. Karnaugh maps work
well for up to six input variables, are usable for up to eight variables. For more than six to eight
variables, simpli¯cation should be by CAD (computer automated design).
Variables Boolean algebra Karnaugh map computer automated
Recommended logic simplification vs number of inputs
1-2
3
4
5-6
7-8
>8
X
X X
X
X
X
X
?
?
X
?
?
?
In theory any of the three methods will work. However, as a practical matter, the above guidelines
work well. We would not normally resort to computer automation to simplify a three input logic
block. We could sooner solve the problem with pencil and paper. However, if we had seven of these
problems to solve, say for a BCD (Binary Coded Decimal) to seven segment decoder, we might want
to automate the process. A BCD to seven segment decoder generates the logic signals to drive a
seven segment LED (light emitting diode) display.
Examples of computer automated design languages for simpli¯cation of logic are PALASM,
ABEL, CUPL, Verilog, and VHDL. These programs accept a hardware descriptor language input ¯le
which is based on Boolean equations and produce an output ¯le describing a reduced (or simpli¯ed)
Boolean solution. We will not require such tools in this chapter. Let's move on to Venn diagrams
as an introduction to Karnaugh maps.
8.2 Venn diagrams and sets
Mathematicians use Venn diagrams to show the logical relationships of sets (collections of objects)
to one another. Perhaps you have already seen Venn diagrams in your algebra or other mathematics
studies. If you have, you may remember overlapping circles and the union and intersection of sets.
We will review the overlapping circles of the Venn diagram. We will adopt the terms OR and AND
instead of union and intersection since that is the terminology used in digital electronics.
The Venn diagram bridges the Boolean algebra from a previous chapter to the Karnaugh Map.
We will relate what you already know about Boolean algebra to Venn diagrams, then transition to
Karnaugh maps.
A set is a collection of objects out of a universe as shown below. The members of the set are
the objects contained within the set. The members of the set usually have something in common;
though, this is not a requirement. Out of the universe of real numbers, for example, the set of all
positive integers f1,2,3...g is a set. The set f3,4,5g is an example of a smaller set, or subset of the
set of all positive integers. Another example is the set of all males out of the universe of college
students. Can you think of some more examples of sets?
8.2. VENN DIAGRAMS AND SETS 221
A
U B
B
A
A
Above left, we have a Venn diagram showing the set A in the circle within the universe U, the
rectangular area. If everything inside the circle is A, then anything outside of the circle is not A.
Thus, above center, we label the rectangular area outside of the circle A as A-not instead of U. We
show B and B-not in a similar manner.
What happens if both A and B are contained within the same universe? We show four possibil-
ities.
A B
A
B
A B A
B
Let's take a closer look at each of the the four possibilities as shown above.
A B
The ¯rst example shows that set A and set B have nothing in common according to the Venn
diagram. There is no overlap between the A and B circular hatched regions. For example, suppose
that sets A and B contain the following members:
set A = f1,2,3,4g set B = f5,6,7,8g
None of the members of set A are contained within set B, nor are any of the members of B
contained within A. Thus, there is no overlap of the circles.
222 CHAPTER 8. KARNAUGH MAPPING
A
B
In the second example in the above Venn diagram, Set A is totally contained within set B How
can we explain this situation? Suppose that sets A and B contain the following members:
set A = f1,2g
set B = f1,2,3,4,5,6,7,8g
All members of set A are also members of set B. Therefore, set A is a subset of Set B. Since all
members of set A are members of set B, set A is drawn fully within the boundary of set B.
There is a ¯fth case, not shown, with the four examples. Hint: it is similar to the last (fourth)
example. Draw a Venn diagram for this ¯fth case.
A B
The third example above shows perfect overlap between set A and set B. It looks like both sets
contain the same identical members. Suppose that sets A and B contain the following:
set A = f1,2,3,4g set B = f1,2,3,4g
Therefore,
Set A = Set B
Sets And B are identically equal because they both have the same identical members. The A and
B regions within the corresponding Venn diagram above overlap completely. If there is any doubt
about what the above patterns represent, refer to any ¯gure above or below to be sure of what the
circular regions looked like before they were overlapped.
8.3. BOOLEAN RELATIONSHIPS ON VENN DIAGRAMS 223
B
A
The fourth example above shows that there is something in common between set A and set B in
the overlapping region. For example, we arbitrarily select the following sets to illustrate our point:
set A = f1,2,3,4g set B = f3,4,5,6g
Set A and Set B both have the elements 3 and 4 in common These elements are the reason for
the overlap in the center common to A and B. We need to take a closer look at this situation
8.3 Boolean Relationships on Venn Diagrams
The fourth example has A partially overlapping B. Though, we will ¯rst look at the whole of all
hatched area below, then later only the overlapping region. Let's assign some Boolean expressions
to the regions above as shown below. Below left there is a red horizontal hatched area for A. There
is a blue vertical hatched area for B.
A+B
A+B
B
A
If we look at the whole area of both, regardless of the hatch style, the sum total of all hatched
areas, we get the illustration above right which corresponds to the inclusive OR function of A, B.
The Boolean expression is A+B. This is shown by the 45o hatched area. Anything outside of the
hatched area corresponds to (A+B)-not as shown above. Let's move on to next part of the fourth
example
The other way of looking at a Venn diagram with overlapping circles is to look at just the part
common to both A and B, the double hatched area below left. The Boolean expression for this
common area corresponding to the AND function is AB as shown below right. Note that everything
outside of double hatched AB is AB-not.
224 CHAPTER 8. KARNAUGH MAPPING
AB
A
B
AB
AB
Note that some of the members of A, above, are members of (AB)'. Some of the members of
B are members of (AB)'. But, none of the members of (AB)' are within the doubly hatched area
AB.
A
B A
B
We have repeated the second example above left. Your ¯fth example, which you previously
sketched, is provided above right for comparison. Later we will ¯nd the occasional element, or group
of elements, totally contained within another group in a Karnaugh map.
Next, we show the development of a Boolean expression involving a complemented variable below.
A
A
B
AB
A
A
B
B
AB
AB
8.3. BOOLEAN RELATIONSHIPS ON VENN DIAGRAMS 225
Example: (above)
Show a Venn diagram for A'B (A-not AND B).
Solution:
Starting above top left we have red horizontal shaded A' (A-not), then, top right, B. Next, lower
left, we form the AND function A'B by overlapping the two previous regions. Most people would
use this as the answer to the example posed. However, only the double hatched A'B is shown far
right for clarity. The expression A'B is the region where both A' and B overlap. The clear region
outside of A'B is (A'B)', which was not part of the posed example.
Let's try something similar with the Boolean OR function.
Example:
Find B'+A
B
B
A
B
Solution:
Above right we start out with B which is complemented to B'. Finally we overlay A on top
of B'. Since we are interested in forming the OR function, we will be looking for all hatched area
regardless of hatch style. Thus, A+B' is all hatched area above right. It is shown as a single hatch
region below left for clarity.
A+B A+B
A+B
A B Double negation
A B DeMorgans theorem A B
Example:
Find (A+B')'
Solution:
226 CHAPTER 8. KARNAUGH MAPPING
The green 45o A+B' hatched area was the result of the previous example. Moving on to a
to,(A+B')' ,the present example, above left, let us ¯nd the complement of A+B', which is the
white clear area above left corresponding to (A+B')'. Note that we have repeated, at right, the
AB' double hatched result from a previous example for comparison to our result. The regions
corresponding to (A+B')' and AB' above left and right respectively are identical. This can be
proven with DeMorgan's theorem and double negation.
This brings up a point. Venn diagrams don't actually prove anything. Boolean algebra is needed
for formal proofs. However, Venn diagrams can be used for veri¯cation and visualization. We have
veri¯ed and visualized DeMorgan's theorem with a Venn diagram.
Example:
What does the Boolean expression A'+B' look like on a Venn Diagram?
A
B
B
B
A
A
A B double hatch
A+B any hatch
A+B clear area
Solution: above ¯gure
Start out with red horizontal hatched A' and blue vertical hatched B' above. Superimpose the
diagrams as shown. We can still see the A' red horizontal hatch superimposed on the other hatch. It
also ¯lls in what used to be part of the B (B-true) circle, but only that part of the B open circle not
common to the A open circle. If we only look at the B' blue vertical hatch, it ¯lls that part of the
open A circle not common to B. Any region with any hatch at all, regardless of type, corresponds
to A'+B'. That is, everything but the open white space in the center.
Example:
What does the Boolean expression (A'+B')' look like on a Venn Diagram?
Solution: above ¯gure, lower left
Looking at the white open space in the center, it is everything NOT in the previous solution of
A'+B', which is (A'+B')'.
8.3. BOOLEAN RELATIONSHIPS ON VENN DIAGRAMS 227
Example:
Show that (A'+B') = AB
Solution: below ¯gure, lower left
A B
A+B = A B = A B
A+B no hatch
AB
A
B
AB
AB
We previously showed on the above right diagram that the white open region is (A'+B')'. On
an earlier example we showed a doubly hatched region at the intersection (overlay) of AB. This is
the left and middle ¯gures repeated here. Comparing the two Venn diagrams, we see that this open
region , (A'+B')', is the same as the doubly hatched region AB (A AND B). We can also prove
that (A'+B')'=AB by DeMorgan's theorem and double negation as shown above.
A
B
C
AB
AC
BC
ABC
Three variable Venn diagram
We show a three variable Venn diagram above with regions A (red horizontal), B (blue vertical),
and, C (green 45o). In the very center note that all three regions overlap representing Boolean
expression ABC. There is also a larger petal shaped region where A and B overlap corresponding
to Boolean expression AB. In a similar manner A and C overlap producing Boolean expression AC.
And B and C overlap producing Boolean expression BC.
228 CHAPTER 8. KARNAUGH MAPPING
Looking at the size of regions described by AND expressions above, we see that region size varies
with the number of variables in the associated AND expression.
² A, 1-variable is a large circular region.
² AB, 2-variable is a smaller petal shaped region.
² ABC, 3-variable is the smallest region.
² The more variables in the AND term, the smaller the region.
8.4 Making a Venn diagram look like a Karnaugh map
Starting with circle A in a rectangular A' universe in ¯gure (a) below, we morph a Venn diagram
into almost a Karnaugh map.
A A
A A
A A
A A
A
A
A A
a b c
d e f
We expand circle A at (b) and (c), conform to the rectangular A' universe at (d), and change
A to a rectangle at (e). Anything left outside of A is A' . We assign a rectangle to A' at (f). Also,
we do not use shading in Karnaugh maps. What we have so far resembles a 1-variable Karnaugh
map, but is of little utility. We need multiple variables.
A A A A
B
B
B
B
a b c
8.4. MAKING A VENN DIAGRAM LOOK LIKE A KARNAUGH MAP 229
Figure (a) above is the same as the previous Venn diagram showing A and A' above except that
the labels A and A' are above the diagram instead of inside the respective regions. Imagine that we
have go through a process similar to ¯gures (a-f) to get a "square Venn diagram" for B and B' as
we show in middle ¯gure (b). We will now superimpose the diagrams in Figures (a) and (b) to get
the result at (c), just like we have been doing for Venn diagrams. The reason we do this is so that
we may observe that which may be common to two overlapping regions¡¡ say where A overlaps
B. The lower right cell in ¯gure (c) corresponds to AB where A overlaps B.
A A
B
B
0 1
0
1
A
B
We don't waste time drawing a Karnaugh map like (c) above, sketching a simpli¯ed version as
above left instead. The column of two cells under A' is understood to be associated with A', and
the heading A is associated with the column of cells under it. The row headed by B' is associated
with the cells to the right of it. In a similar manner B is associated with the cells to the right of it.
For the sake of simplicity, we do not delineate the various regions as clearly as with Venn diagrams.
The Karnaugh map above right is an alternate form used in most texts. The names of the
variables are listed next to the diagonal line. The A above the diagonal indicates that the variable
A (and A') is assigned to the columns. The 0 is a substitute for A', and the 1 substitutes for A.
The B below the diagonal is associated with the rows: 0 for B', and 1 for B
Example:
Mark the cell corresponding to the Boolean expression AB in the Karnaugh map above with a
1
A A
B
B
A A
B
B 1
A A
B
B 1
Solution:
Shade or circle the region corresponding to A. Then, shade or enclose the region corresponding
to B. The overlap of the two regions is AB. Place a 1 in this cell. We do not necessarily enclose the
A and B regions as at above left.
230 CHAPTER 8. KARNAUGH MAPPING
A
A
B B
C C C
A
A
C C C
B B
We develop a 3-variable Karnaugh map above, starting with Venn diagram like regions. The
universe (inside the black rectangle) is split into two narrow narrow rectangular regions for A' and
A. The variables B' and B divide the universe into two square regions. C occupies a square region
in the middle of the rectangle, with C' split into two vertical rectangles on each side of the C square.
In the ¯nal ¯gure, we superimpose all three variables, attempting to clearly label the various
regions. The regions are less obvious without color printing, more obvious when compared to the
other three ¯gures. This 3-variable K-Map (Karnaugh map) has 23 = 8 cells, the small squares
within the map. Each individual cell is uniquely identi¯ed by the three Boolean Variables (A, B,
C). For example, ABC' uniquely selects the lower right most cell(*), A'B'C' selects the upper left
most cell (x).
A
A
C C C
B B
A
A
B C B C B C B C
*
x
We don't normally label the Karnaugh map as shown above left. Though this ¯gure clearly
shows map coverage by single boolean variables of a 4-cell region. Karnaugh maps are labeled like
the illustration at right. Each cell is still uniquely identi¯ed by a 3-variable product term, a Boolean
8.5. KARNAUGH MAPS, TRUTH TABLES, AND BOOLEAN EXPRESSIONS 231
AND expression. Take, for example, ABC' following the A row across to the right and the BC'
column down, both intersecting at the lower right cell ABC'. See (*) above ¯gure.
A
C B C BC BC
A
0
1
B A 00 01 1110
BC
The above two di®erent forms of a 3-variable Karnaugh map are equivalent, and is the ¯nal form
that it takes. The version at right is a bit easier to use, since we do not have to write down so many
boolean alphabetic headers and complement bars, just 1s and 0s Use the form of map on the right
and look for the the one at left in some texts. The column headers on the left B'C', B'C, BC,
BC' are equivalent to 00, 01, 11, 10 on the right. The row headers A, A' are equivalent to 0, 1
on the right map.
8.5 Karnaugh maps, truth tables, and Boolean expressions
Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at Bell Labs in
1953 while designing digital logic based telephone switching circuits.
Now that we have developed the Karnaugh map with the aid of Venn diagrams, let's put it to
use. Karnaugh maps reduce logic functions more quickly and easily compared to Boolean algebra.
By reduce we mean simplify, reducing the number of gates and inputs. We like to simplify logic to
a lowest cost form to save costs by elimination of components. We de¯ne lowest cost as being the
lowest number of gates with the lowest number of inputs per gate.
Given a choice, most students do logic simpli¯cation with Karnaugh maps rather than Boolean
algebra once they learn this tool.
232 CHAPTER 8. KARNAUGH MAPPING
B Output
0 0
0 1
1 0
1 1
A 0 1
0
1
A
B
a
b
c
d
a b
c d
B
A
Output
···
unspecified logic
B
A 1
CR1
CR1 CR2 . . .
...
L1 L2
CR2
Output = ABC + ABC + . . . ABC
..
.
We show ¯ve individual items above, which are just di®erent ways of representing the same thing:
an arbitrary 2-input digital logic function. First is relay ladder logic, then logic gates, a truth table,
a Karnaugh map, and a Boolean equation. The point is that any of these are equivalent. Two inputs
A and B can take on values of either 0 or 1, high or low, open or closed, True or False, as the case
may be. There are 22= 4 combinations of inputs producing an output. This is applicable to all ¯ve
examples.
These four outputs may be observed on a lamp in the relay ladder logic, on a logic probe on the
gate diagram. These outputs may be recorded in the truth table, or in the Karnaugh map. Look
at the Karnaugh map as being a rearranged truth table. The Output of the Boolean equation may
be computed by the laws of Boolean algebra and transfered to the truth table or Karnaugh map.
Which of the ¯ve equivalent logic descriptions should we use? The one which is most useful for the
task to be accomplished.
8.5. KARNAUGH MAPS, TRUTH TABLES, AND BOOLEAN EXPRESSIONS 233
A B Output
0 0
0 1
1 0
1 1
0 1
0
1
A
B
a
b
c
d
a b
c d
The outputs of a truth table correspond on a one-to-one basis to Karnaugh map entries. Starting
at the top of the truth table, the A=0, B=0 inputs produce an output ®. Note that this same output
® is found in the Karnaugh map at the A=0, B=0 cell address, upper left corner of K-map where
the A=0 row and B=0 column intersect. The other truth table outputs ¯, Â, ± from inputs AB=01,
10, 11 are found at corresponding K-map locations.
Below, we show the adjacent 2-cell regions in the 2-variable K-map with the aid of previous
rectangular Venn diagram like Boolean regions.
0 1
0
1
A
B
a b
c d
A
A
B B
0 1
0
1
A
B
a b
c d
0 1
0
1
A
B
a b
c d
0 1
0
1
A
B
a b
c d
A
A
B B
Cells ® and  are adjacent in the K-map as ellipses in the left most K-map below. Referring to
the previous truth table, this is not the case. There is another truth table entry (¯) between them.
Which brings us to the whole point of the organizing the K-map into a square array, cells with any
Boolean variables in common need to be close to one another so as to present a pattern that jumps
out at us. For cells ® and  they have the Boolean variable B' in common. We know this because
B=0 (same as B') for the column above cells ® and Â. Compare this to the square Venn diagram
above the K-map.
A similar line of reasoning shows that ¯ and ± have Boolean B (B=1) in common. Then, ® and ¯
have Boolean A' (A=0) in common. Finally, Â and ± have Boolean A (A=1) in common. Compare
the last two maps to the middle square Venn diagram.
To summarize, we are looking for commonality of Boolean variables among cells. The Karnaugh
map is organized so that we may see that commonality. Let's try some examples.
234 CHAPTER 8. KARNAUGH MAPPING
A B Output
0 0
0 1
1 0
1 1
0 1
0
1
A B
0
0
1
1
Example:
Transfer the contents of the truth table to the Karnaugh map above.
A B Output
0 0
0 1
1 0
1 1
0 1
0
1
A B
0
0
1
1
1
1
A=
B=
A=
B=
0
1
11
Solution:
The truth table contains two 1s. the K- map must have both of them. locate the ¯rst 1 in the
2nd row of the truth table above.
² note the truth table AB address
² locate the cell in the K-map having the same address
² place a 1 in that cell
Repeat the process for the 1 in the last line of the truth table.
Example:
For the Karnaugh map in the above problem, write the Boolean expression. Solution is below.
8.5. KARNAUGH MAPS, TRUTH TABLES, AND BOOLEAN EXPRESSIONS 235
0 1
0
1
A B
1
1
A
A
B B
Out = B
Solution:
Look for adjacent cells, that is, above or to the side of a cell. Diagonal cells are not adjacent.
Adjacent cells will have one or more Boolean variables in common.
² Group (circle) the two 1s in the column
² Find the variable(s) top and/or side which are the same for the group, Write this as the
Boolean result. It is B in our case.
² Ignore variable(s) which are not the same for a cell group. In our case A varies, is both 1 and
0, ignore Boolean A.
² Ignore any variable not associated with cells containing 1s. B' has no ones under it. Ignore B'
² Result Out = B
This might be easier to see by comparing to the Venn diagrams to the right, speci¯cally the B
column.
Example:
Write the Boolean expression for the Karnaugh map below.
0 1
0
1
A B
1 1
A
A
B B
Out = A
Solution: (above)
² Group (circle) the two 1's in the row
² Find the variable(s) which are the same for the group, Out = A'
236 CHAPTER 8. KARNAUGH MAPPING
Example:
For the Truth table below, transfer the outputs to the Karnaugh, then write the Boolean expres-
sion for the result.
A B Output
0 0
0 1
1 0
1 1
0 1
0
1
A B
1
1
1
1
1 1
0 1
0
1
A B
1
1 1
Output= A + B
0
0 1
0
1
A B
1
1 1
Wrong Output= AB + B
Solution:
Transfer the 1s from the locations in the Truth table to the corresponding locations in the K-map.
² Group (circle) the two 1's in the column under B=1
² Group (circle) the two 1's in the row right of A=1
² Write product term for ¯rst group = B
² Write product term for second group = A
² Write Sum-Of-Products of above two terms Output = A+B
The solution of the K-map in the middle is the simplest or lowest cost solution. A less desirable
solution is at far right. After grouping the two 1s, we make the mistake of forming a group of 1-cell.
The reason that this is not desirable is that:
² The single cell has a product term of AB'
² The corresponding solution is Output = AB' + B
² This is not the simplest solution
The way to pick up this single 1 is to form a group of two with the 1 to the right of it as shown in the
lower line of the middle K-map, even though this 1 has already been included in the column group
(B). We are allowed to re-use cells in order to form larger groups. In fact, it is desirable because it
leads to a simpler result.
We need to point out that either of the above solutions, Output or Wrong Output, are logically
correct. Both circuits yield the same output. It is a matter of the former circuit being the lowest
cost solution.
Example:
8.5. KARNAUGH MAPS, TRUTH TABLES, AND BOOLEAN EXPRESSIONS 237
Fill in the Karnaugh map for the Boolean expression below, then write the Boolean expression
for the result.
0 1
0
1
A B
1
1 1
0 1
0
1
A B
1
1 1
Output= A + B
Out= AB + AB + AB A
01 10 11
Solution: (above)
The Boolean expression has three product terms. There will be a 1 entered for each product
term. Though, in general, the number of 1s per product term varies with the number of variables
in the product term compared to the size of the K-map. The product term is the address of the cell
where the 1 is entered. The ¯rst product term, A'B, corresponds to the 01 cell in the map. A 1 is
entered in this cell. The other two P-terms are entered for a total of three 1s
Next, proceed with grouping and extracting the simpli¯ed result as in the previous truth table
problem.
Example:
Simplify the logic diagram below.
B
A
A B
A
B
Out
Solution: (Figure below)
² Write the Boolean expression for the original logic diagram as shown below
² Transfer the product terms to the Karnaugh map
² Form groups of cells as in previous examples
² Write Boolean expression for groups as in previous examples
² Draw simpli¯ed logic diagram
238 CHAPTER 8. KARNAUGH MAPPING
0 1
0
1
A B
1
1 1
0 1
0
1
A B
1
1 1
Out= A + B
Out= AB + AB + AB A
01 10 11
B
AB
AB
A
AB
A
B
A
B
Out
Out
A
B
Example:
Simplify the logic diagram below.
0 1
0
1
A B
1
1
Out= AB + AB
01 10
B
AB
A
AB
A
B
Out Out
Exclusive-OR
A
B
Solution:
² Write the Boolean expression for the original logic diagram shown above
² Transfer the product terms to the Karnaugh map.
² It is not possible to form groups.
² No simpli¯cation is possible; leave it as it is.
No logic simpli¯cation is possible for the above diagram. This sometimes happens. Neither
the methods of Karnaugh maps nor Boolean algebra can simplify this logic further. We show an
Exclusive-OR schematic symbol above; however, this is not a logical simpli¯cation. It just makes a
schematic diagram look nicer. Since it is not possible to simplify the Exclusive-OR logic and it is
widely used, it is provided by manufacturers as a basic integrated circuit (7486).
8.6 Logic simpli¯cation with Karnaugh maps
The logic simpli¯cation examples that we have done so could have been performed with Boolean
algebra about as quickly. Real world logic simpli¯cation problems call for larger Karnaugh maps so
that we may do serious work. We will work some contrived examples in this section, leaving most of
the real world applications for the Combinatorial Logic chapter. By contrived, we mean examples
8.6. LOGIC SIMPLIFICATION WITH KARNAUGH MAPS 239
which illustrate techniques. This approach will develop the tools we need to transition to the more
complex applications in the Combinatorial Logic chapter.
We show our previously developed Karnaugh map. We will use the form on the right
A
C B C BC BC
A
0
1
B A 00 01 1110
BC
Note the sequence of numbers across the top of the map. It is not in binary sequence which
would be 00, 01, 10, 11. It is 00, 01, 11 10, which is Gray code sequence. Gray code sequence
only changes one binary bit as we go from one number to the next in the sequence, unlike binary.
That means that adjacent cells will only vary by one bit, or Boolean variable. This is what we need
to organize the outputs of a logic function so that we may view commonality. Moreover, the column
and row headings must be in Gray code order, or the map will not work as a Karnaugh map. Cells
sharing common Boolean variables would no longer be adjacent, nor show visual patterns. Adjacent
cells vary by only one bit because a Gray code sequence varies by only one bit.
If we sketch our own Karnaugh maps, we need to generate Gray code for any size map that we
may use. This is how we generate Gray code of any size.
240 CHAPTER 8. KARNAUGH MAPPING
00
01
1
0
0
1
1
0
0
1
0
1
00
01
11
10
00
01
11
10
00
01
11
10
10
11
01
00
000
001
011
010
10
11
01
00
000
001
011
010
110
111
101
100
How to generate Gray code.
1. Write 0,1 in a column.
2. Draw a mirror under the column.
3. Reflect the numbers about the mirror.
4. Distinguish the numbers above the mirror with leading zeros.
5. Distinguish those below the mirror with
leading ones.
6. Finished 2-bit Gray code.
7. Need 3-bit Gray code? Draw
mirror under column of four
2-bit codes,reflect about
mirror.
8. Distinguish upper 4-numbers with leading zeros.
9. Distinguish lower 4-numbers with leading ones.
Note that the Gray code sequence, above right, only varies by one bit as we go down the list, or
bottom to top up the list. This property of Gray code is often useful in digital electronics in general.
In particular, it is applicable to Karnaugh maps.
Let us move on to some examples of simpli¯cation with 3-variable Karnaugh maps. We show
how to map the product terms of the unsimpli¯ed logic to the K-map. We illustrate how to identify
groups of adjacent cells which leads to a Sum-of-Products simpli¯cation of the digital logic.
10
1
00 0111
0
A
BC
1 1
Out= A BC + ABC
× Out= A B ×
Above we, place the 1's in the K-map for each of the product terms, identify a group of two,
then write a p-term (product term) for the sole group as our simpli¯ed result.
8.6. LOGIC SIMPLIFICATION WITH KARNAUGH MAPS 241
10
1
00 0111
0
A
BC
1 1 1 1
Out= ABC + ABC + AB C + A BC
Out= A ×
Mapping the four product terms above yields a group of four covered by Boolean A'
10
1
00 0111
0
A
BC
1 1
1 1
Out= C
Out= A BC + A B C + A B C + A B C
×
Mapping the four p-terms yields a group of four, which is covered by one variable C.
10
1
00 0111
0
A
BC
1 1 1 1
1 1
Out= A + B
Out= A B C +A B C+AB C+A B C +ABC+A BC
After mapping the six p-terms above, identify the upper group of four, pick up the lower two
cells as a group of four by sharing the two with two more from the other group. Covering these two
with a group of four gives a simpler result. Since there are two groups, there will be two p-terms in
the Sum-of-Products result A'+B
00 0111
10
1
0
A
BC
1
1
Out= A BC + AB C
Out= B C ×
242 CHAPTER 8. KARNAUGH MAPPING
The two product terms above form one group of two and simpli¯es to BC
00 0111
10
1
0
A
BC
1 1
1 1
Out= A BC + AB C + ABC + AB C
Out= B ×
Mapping the four p-terms yields a single group of four, which is B
00 0111
10
1
0
A
BC
1
1 1
1
Out= A BC + AB C + ABC + AB C
Out= C
0001
11
10
1
1 1
1
1
1 1
1
×
Mapping the four p-terms above yields a group of four. Visualize the group of four by rolling up
the ends of the map to form a cylinder, then the cells are adjacent. We normally mark the group of
four as above left. Out of the variables A, B, C, there is a common variable: C'. C' is a 0 over all
four cells. Final result is C'.
00 0111
10
1
0
A
BC
1 1
1 1
Out= A + C
1 1
Out= A BC+A B C+A B C+ABC +A BC +A B C
The six cells above from the unsimpli¯ed equation can be organized into two groups of four.
These two groups should give us two p-terms in our simpli¯ed result of A' + C'.
Below, we revisit the Toxic Waste Incinerator from the Boolean algebra chapter. See Boolean
algebra chapter for details on this example. We will simplify the logic using a Karnaugh map.
8.6. LOGIC SIMPLIFICATION WITH KARNAUGH MAPS 243
Output = ABC + ABC + ABC + ABC
A B C
ABC
ABC
ABC
ABC
10
1
00 0111
0
A
BC
1
1 1 1
Output = AB + BC + AC
The Boolean equation for the output has four product terms. Map four 1's corresponding to the
p-terms. Forming groups of cells, we have three groups of two. There will be three p-terms in the
simpli¯ed result, one for each group. See "Toxic Waste Incinerator", Boolean algebra chapter for a
gate diagram of the result, which is reproduced below.
A B C
Output = AB + BC + AC
AB
BC
AC
Below we repeat the Boolean algebra simpli¯cation of Toxic waste incinerator for comparison.
244 CHAPTER 8. KARNAUGH MAPPING
ABC + ABC + ABC + ABC
Factoring BC out of 1st and 4th terms
BC(A + A) + ABC + ABC
Applying identity A + A = 1
BC(1) + ABC + ABC
Applying identity 1A = A
BC + ABC + ABC
Factoring B out of 1st and 3rd terms
B(C + AC) + ABC
Applying rule A + AB = A + B to
the C + AC term
B(C + A) + ABC
Distributing terms
BC + AB + ABC
Factoring A out of 2nd and 3rd terms
BC + A(B + BC)
Applying rule A + AB = A + B to
the B + BC term
BC + A(B + C)
Distributing terms
BC + AB + AC
or
AB + BC + AC
Simplified result
Below we repeat the Toxic waste incinerator Karnaugh map solution for comparison to the above
Boolean algebra simpli¯cation. This case illustrates why the Karnaugh map is widely used for logic
simpli¯cation.
00 0111
10
1
0
A
BC
1
1 1 1
Output = AB + BC + AC
8.7. LARGER 4-VARIABLE KARNAUGH MAPS 245
The Karnaugh map method looks easier than the previous page of boolean algebra.
8.7 Larger 4-variable Karnaugh maps
Knowing how to generate Gray code should allow us to build larger maps. Actually, all we need to
do is look at the left to right sequence across the top of the 3-variable map, and copy it down the
left side of the 4-variable map. See below.
00 01 11 10
00
01
11
10
AB
CD
×
The following four variable Karnaugh maps illustrate reduction of Boolean expressions too tedious
for Boolean algebra. Reductions could be done with Boolean algebra. However, the Karnaugh map
is faster and easier, especially if there are many logic reductions to do.
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1 1 1
×
Out= AB + CD
Out= ABCD+ABCD+ ABCD+ABCD+ABC D+ABCD+ABCD
The above Boolean expression has seven product terms. They are mapped top to bottom and
left to right on the K-map above. For example, the ¯rst P-term A'B'CD is ¯rst row 3rd cell,
corresponding to map location A=0, B=0, C=1, D=1. The other product terms are placed
in a similar manner. Encircling the largest groups possible, two groups of four are shown above.
The dashed horizontal group corresponds the the simpli¯ed product term AB. The vertical group
corresponds to Boolean CD. Since there are two groups, there will be two product terms in the
Sum-Of-Products result of Out=AB+CD.
Fold up the corners of the map below like it is a napkin to make the four cells physically adjacent.
246 CHAPTER 8. KARNAUGH MAPPING
×
00 01 11 10
00
01
11
10
AB
CD
1 1
1 1
Out= BD
Out= ABCD + ABCD + ABC D + ABCD
1 1
1 1
The four cells above are a group of four because they all have the Boolean variables B' and D'
in common. In other words, B=0 for the four cells, and D=0 for the four cells. The other variables
(A, B) are 0 in some cases, 1 in other cases with respect to the four corner cells. Thus, these
variables (A, B) are not involved with this group of four. This single group comes out of the map
as one product term for the simpli¯ed result: Out=B'C'
For the K-map below, roll the top and bottom edges into a cylinder forming eight adjacent cells.
00 01 11 10
00
01
11
10
AB
CD
1 1 1 1
1 1 1 1
×
Out= B
Out= A B CD + AB CD + A BC D + A BC D
+ A B CD +A BC D + A BC D + AB C D
The above group of eight has one Boolean variable in common: B=0. Therefore, the one group
of eight is covered by one p-term: B'. The original eight term Boolean expression simpli¯es to
Out=B'
The Boolean expression below has nine p-terms, three of which have three Booleans instead of
four. The di®erence is that while four Boolean variable product terms cover one cell, the three
Boolean p-terms cover a pair of cells each.
8.7. LARGER 4-VARIABLE KARNAUGH MAPS 247
00 01 11 10
00
01
11
10
AB
CD
1 1 1 1
1 1 1 1
1
1
1
1
×
Out= ABCD + ABCD + AB CD + ABCD
+ BCD + BCD + ABCD + A BD + ABCD
Out= B + D
00 01 11 10
00
01
11
10
AB
CD
1 1 1 1
1 1 1 1
1
1
1
1
B
D
The six product terms of four Boolean variables map in the usual manner above as single cells.
The three Boolean variable terms (three each) map as cell pairs, which is shown above. Note that
we are mapping p-terms into the K-map, not pulling them out at this point.
For the simpli¯cation, we form two groups of eight. Cells in the corners are shared with both
groups. This is ¯ne. In fact, this leads to a better solution than forming a group of eight and a
group of four without sharing any cells. Final Solution is Out=B'+D'
Below we map the unsimpli¯ed Boolean expression to the Karnaugh map.
00 01 11 10
00
01
11
10
AB
CD
1
1 1
Out= BCD + A B D + A B C D
Out= A BC D + ABC D + ABC D + ABCD
1
×
Above, three of the cells form into a groups of two cells. A fourth cell cannot be combined with
anything, which often happens in "real world" problems. In this case, the Boolean p-term ABCD
is unchanged in the simpli¯cation process. Result: Out= B'C'D'+A'B'D'+ABCD
Often times there is more than one minimum cost solution to a simpli¯cation problem. Such is
the case illustrated below.
248 CHAPTER 8. KARNAUGH MAPPING
Out= B C D + AC D + BC D + AC D
Out= AB CD + A B CD + A B CD + AB CD
+ A BC D + A BC D + AB C D + AB CD
×
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1 1
1
1
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1 1
1
1
Out= A B C + AB D + AB C + AB D
Both results above have four product terms of three Boolean variable each. Both are equally
valid minimal cost solutions. The di®erence in the ¯nal solution is due to how the cells are grouped
as shown above. A minimal cost solution is a valid logic design with the minimum number of gates
with the minimum number of inputs.
Below we map the unsimpli¯ed Boolean equation as usual and form a group of four as a ¯rst
simpli¯cation step. It may not be obvious how to pick up the remaining cells.
AB
CD
1
Out= AC + AD + B C + BD
Out= A BC D + A B C D + ABCD
+ A BC D + ABC D + A BC D
+ A BC D + ABC D + A B C D
1
1
1
1
×
1
1 1 1
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10
Pick up three more cells in a group of four, center above. There are still two cells remaining. the
minimal cost method to pick up those is to group them with neighboring cells as groups of four as
at above right.
On a cautionary note, do not attempt to form groups of three. Groupings must be powers of 2,
that is, 1, 2, 4, 8 ...
Below we have another example of two possible minimal cost solutions. Start by forming a couple
of groups of four after mapping the cells.
8.8. MINTERM VS MAXTERM SOLUTION 249
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
×
Out= C D + C D+ ABC
Out= ABCD+ABCD+ ABCD+ABCD+ABC D
+A BCD + ABCD + AB CD + A BCD
1
1
1
1
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1
1
1
Out= CD + CD+ ABD
The two solutions depend on whether the single remaining cell is grouped with the ¯rst or the
second group of four as a group of two cells. That cell either comes out as either ABC' or ABD,
your choice. Either way, this cell is covered by either Boolean product term. Final results are shown
above.
Below we have an example of a simpli¯cation using the Karnaugh map at left or Boolean algebra
at right. Plot C' on the map as the area of all cells covered by address C=0, the 8-cells on the left
of the map. Then, plot the single ABCD cell. That single cell forms a group of 2-cell as shown,
which simpli¯es to P-term ABD, for an end result of Out = C' + ABD.
00 01 11 10
00
01
11
10
AB
CD
1 1 1
×
Out= C + ABD
Out= C + ABCD
1 1
1 1
1 1
Applying rule A + A B = A + B to
the C + ABCD term
Out= C + ABC D
Out= C + ABD
Simplification by Boolean
Algebra
This (above) is a rare example of a four variable problem that can be reduced with Boolean
algebra without a lot of work, assuming that you remember the theorems.
8.8 Minterm vs maxterm solution
So far we have been ¯nding Sum-Of-Product (SOP) solutions to logic reduction problems. For each
of these SOP solutions, there is also a Product-Of-Sums solution (POS), which could be more useful,
250 CHAPTER 8. KARNAUGH MAPPING
depending on the application. Before working a Product-Of-Sums solution, we need to introduce
some new terminology. The procedure below for mapping product terms is not new to this chapter.
We just want to establish a formal procedure for minterms for comparison to the new procedure for
maxterms.
10
1
00 0111
0
A
BC
Out= AB C
0
10
1
00 0111
0
A
BC
0
1
1
Out= AB C
0 0 0
0 0 0 0 0 0
0 0 0
Numeric= 1 1 1
Minterm= A B C
Out= AB C Out= AB C
Minterm= A B C
Numeric= 0 1 0
A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s for all
other cells in a Karnaugh map, or truth table. If a minterm has a single 1 and the remaining cells as
0s, it would appear to cover a minimum area of 1s. The illustration above left shows the minterm
ABC, a single product term, as a single 1 in a map that is otherwise 0s. We have not shown
the 0s in our Karnaugh maps up to this point, as it is customary to omit them unless speci¯cally
needed. Another minterm A'BC' is shown above right. The point to review is that the address of
the cell corresponds directly to the minterm being mapped. That is, the cell 111 corresponds to the
minterm ABC above left. Above right we see that the minterm A'BC' corresponds directly to the
cell 010. A Boolean expression or map may have multiple minterms.
Referring to the above ¯gure, Let's summarize the procedure for placing a minterm in a K-map:
² Identify the minterm (product term) term to be mapped.
² Write the corresponding binary numeric value.
² Use binary value as an address to place a 1 in the K-map
² Repeat steps for other minterms (P-terms within a Sum-Of-Products).
Out= AB C +ABC
00 0111
10
1
0
A
BC
1
0 0 0
0 0 0
. 1
Numeric= 0 1 0 111
Minterm= A B C ABC
Out= AB C + ABC
8.8. MINTERM VS MAXTERM SOLUTION 251
A Boolean expression will more often than not consist of multiple minterms corresponding to
multiple cells in a Karnaugh map as shown above. The multiple minterms in this map are the
individual minterms which we examined in the previous ¯gure above. The point we review for
reference is that the 1s come out of the K-map as a binary cell address which converts directly to
one or more product terms. By directly we mean that a 0 corresponds to a complemented variable,
and a 1 corresponds to a true variable. Example: 010 converts directly to A'BC'. There was no
reduction in this example. Though, we do have a Sum-Of-Products result from the minterms.
Referring to the above ¯gure, Let's summarize the procedure for writing the Sum-Of-Products
reduced Boolean equation from a K-map:
² Form largest groups of 1s possible covering all minterms. Groups must be a power of 2.
² Write binary numeric value for groups.
² Convert binary value to a product term.
² Repeat steps for other groups. Each group yields a p-terms within a Sum-Of-Products.
Nothing new so far, a formal procedure has been written down for dealing with minterms. This
serves as a pattern for dealing with maxterms.
Next we attack the Boolean function which is 0 for a single cell and 1s for all others.
00 0111
10
1
0
A
BC
0 1 1 1
1 1 1 1
Numeric = 1 1 1
Maxterm = A + B + C
Out = ( A + B + C )
Complement = 0 0 0
. .
A maxterm is a Boolean expression resulting in a 0 for the output of a single cell expression,
and 1s for all other cells in the Karnaugh map, or truth table. The illustration above left shows the
maxterm (A+B+C), a single sum term, as a single 0 in a map that is otherwise 1s. If a maxterm
has a single 0 and the remaining cells as 1s, it would appear to cover a maximum area of 1s.
There are some di®erences now that we are dealing with something new, maxterms. The maxterm
is a 0, not a 1 in the Karnaugh map. A maxterm is a sum term, (A+B+C) in our example, not a
product term.
It also looks strange that (A+B+C) is mapped into the cell 000. For the equation Out=(A+B+C)=0,
all three variables (A, B, C) must individually be equal to 0. Only (0+0+0)=0 will equal 0. Thus
we place our sole 0 for minterm (A+B+C) in cell A,B,C=000 in the K-map, where the inputs
are all0 . This is the only case which will give us a 0 for our maxterm. All other cells contain 1s
because any input values other than ((0,0,0) for (A+B+C) yields 1s upon evaluation.
Referring to the above ¯gure, the procedure for placing a maxterm in the K-map is:
252 CHAPTER 8. KARNAUGH MAPPING
² Identify the Sum term to be mapped.
² Write corresponding binary numeric value.
² Form the complement
² Use the complement as an address to place a 0 in the K-map
² Repeat for other maxterms (Sum terms within Product-of-Sums expression).
00 0111
10
1
0
A
BC
0
1 1
1 1
1
1
1
Numeric = 0 0 0
Maxterm = A + B + C
Out = ( A + B + C )
Complement = 1 1 1
. .
Another maxterm A'+B'+C' is shown above. Numeric 000 corresponds to A'+B'+C'. The
complement is 111. Place a 0 for maxterm (A'+B'+C') in this cell (1,1,1) of the K-map as shown
above.
Why should (A'+B'+C') cause a 0 to be in cell 111? When A'+B'+C' is (1'+1'+1'), all
1s in, which is (0+0+0) after taking complements, we have the only condition that will give us a
0. All the 1s are complemented to all 0s, which is 0 when ORed.
00 0111
10
1
0
A
BC
1
0 0 1 1
1 1 1
Out = ( A +B +C )( A + B + C)
Maxterm= (A + B + C )
Numeric= 1 1 1
Complement= 0 0 0
Maxterm= (A +B + C )
Numeric= 1 1 0
Complement= 0 0 1
A Boolean Product-Of-Sums expression or map may have multiple maxterms as shown above.
Maxterm (A+B+C) yields numeric 111 which complements to 000, placing a 0 in cell (0,0,0).
Maxterm (A+B+C') yields numeric 110 which complements to 001, placing a 0 in cell (0,0,1).
Now that we have the k-map setup, what we are really interested in is showing how to write a
Product-Of-Sums reduction. Form the 0s into groups. That would be a group of two below. Write
the binary value corresponding to the sum-term which is (0,0,X). Both A and B are 0 for the group.
8.8. MINTERM VS MAXTERM SOLUTION 253
But, C is both 0 and 1 so we write an X as a place holder for C. Form the complement (1,1,X).
Write the Sum-term (A+B) discarding the C and the X which held its' place. In general, expect to
have more sum-terms multiplied together in the Product-Of-Sums result. Though, we have a simple
example here.
00 0111
10
1
0
A
BC
1
Out =(A + B )
0 0 1
×
1
1 1 1
A B C = 0 0 X
Complement = 1 1 X
Sum-term =(A + B)
Out = ( A +B + C )( A +B + C )
×
Let's summarize the procedure for writing the Product-Of-Sums Boolean reduction for a K-map:
² Form largest groups of 0s possible, covering all maxterms. Groups must be a power of 2.
² Write binary numeric value for group.
² Complement binary numeric value for group.
² Convert complement value to a sum-term.
² Repeat steps for other groups. Each group yields a sum-term within a Product-Of-Sums result.
Example:
Simplify the Product-Of-Sums Boolean expression below, providing a result in POS form.
Out= ( A + B + C +D )( A + B +C + D ) ( A +B + C +D )( A + B +C + D)
( A +B + C + D)(A + B + C + D )(A + B + C + D )
Solution:
Transfer the seven maxterms to the map below as 0s. Be sure to complement the input variables
in ¯nding the proper cell location.
254 CHAPTER 8. KARNAUGH MAPPING
00 01 11 10
00
01
11
10
×
Out= (A +B+C+D )( A+B+C+ D)(A+B +C+D)( A+ B+C+D)
(A+B+C +D)(A+B+C +D)( A +B+C+D)
0
0
0
0
0
0
0
AB
CD
We map the 0s as they appear left to right top to bottom on the map above. We locate the last
three maxterms with leader lines..
Once the cells are in place above, form groups of cells as shown below. Larger groups will give
a sum-term with fewer inputs. Fewer groups will yield fewer sum-terms in the result.
00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
Out= (B+C+ D)(A+C+ D)( C+D )
AB
CD
ABCD = XX10 > XX01 > (C+D )
ABCD = 0X01 > 1X10 > ( A+ C+D )
ABCD = X001 > X110 > ( B+ C+D )
input complement Sum-term
We have three groups, so we expect to have three sum-terms in our POS result above. The group
of 4-cells yields a 2-variable sum-term. The two groups of 2-cells give us two 3-variable sum-terms.
Details are shown for how we arrived at the Sum-terms above. For a group, write the binary group
input address, then complement it, converting that to the Boolean sum-term. The ¯nal result is
product of the three sums.
Example:
Simplify the Product-Of-Sums Boolean expression below, providing a result in SOP form.
Out= ( A + B + C + D )( A + B +C + D ) ( A +B + C +D )( A + B +C + D)
( A +B + C + D)(A + B + C +D )( A + B +C + D )
Solution:
8.8. MINTERM VS MAXTERM SOLUTION 255
This looks like a repeat of the last problem. It is except that we ask for a Sum-Of-Products
Solution instead of the Product-Of-Sums which we just ¯nished. Map the maxterm 0s from the
Product-Of-Sums given as in the previous problem, below left.
00 01 11 10
00
01
11
10
×
Out= (A +B+C+D )( A+B+C+ D)(A+B +C+D)( A+ B+C+D)
(A+B+C +D)(A+B+C +D)( A +B+C+D)
0
0
0
0
0
0
0
AB
CD
00 01 11 10
00
01
11
10
0
0
0
0
0
0
0
AB
CD
1 1
1 1
1 1 1
1 1
Then ¯ll in the implied 1s in the remaining cells of the map above right.
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1
1
1
Out= C D + CD+ A BD
0
0
0
0
0
0
0
.
Form groups of 1s to cover all 1s. Then write the Sum-Of-Products simpli¯ed result as in the
previous section of this chapter. This is identical to a previous problem.
256 CHAPTER 8. KARNAUGH MAPPING
00 01 11 10
00
01
11
10
Out= ( A + B+ C +D )( A+ B +C + D) ( A +B + C+ D )(A + B+ C + D)
( A +B + C+ D)(A + B+ C +D )( A + B +C + D )
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1
1
1
Out= C D + C D + A B D
0
0
0
0
0
0
0
Out= (B+ C + D)(A+ C + D)( C+ D )
AB
CD
Above we show both the Product-Of-Sums solution, from the previous example, and the Sum-
Of-Products solution from the current problem for comparison. Which is the simpler solution? The
POS uses 3-OR gates and 1-AND gate, while the SOP uses 3-AND gates and 1-OR gate. Both use
four gates each. Taking a closer look, we count the number of gate inputs. The POS uses 8-inputs;
the SOP uses 7-inputs. By the de¯nition of minimal cost solution, the SOP solution is simpler. This
is an example of a technically correct answer that is of little use in the real world.
The better solution depends on complexity and the logic family being used. The SOP solution
is usually better if using the TTL logic family, as NAND gates are the basic building block, which
works well with SOP implementations. On the other hand, A POS solution would be acceptable
when using the CMOS logic family since all sizes of NOR gates are available.
Out= (B + C + D )(A + C+D)( C+D) Out= CD + C D + A B D
C
D
A
B
Out
D
C
B
A
Out
The gate diagrams for both cases are shown above, Product-Of-Sums left, and Sum-Of-Products
right.
Below, we take a closer look at the Sum-Of-Products version of our example logic, which is
repeated at left.
8.8. MINTERM VS MAXTERM SOLUTION 257
Out= C D + C D + ABD
C
D
A
B
Out
Out= CD + C D+ A BD
C
D
A
B
Out
Above all AND gates at left have been replaced by NAND gates at right.. The OR gate at the
output is replaced by a NAND gate. To prove that AND-OR logic is equivalent to NAND-NAND
logic, move the inverter invert bubbles at the output of the 3-NAND gates to the input of the ¯nal
NAND as shown in going from above right to below left.
C
D
A
B
Out
Out
X Out
Y
Z
X
Y
Z
Out= X+Y+Z
Out= X Y Z
Out= X+ Y + Z
Out= X+Y+Z
DeMorgans
Double negation
Above right we see that the output NAND gate with inverted inputs is logically equivalent to an
OR gate by DeMorgan's theorem and double negation. This information is useful in building digital
logic in a laboratory setting where TTL logic family NAND gates are more readily available in a
wide variety of con¯gurations than other types.
The Procedure for constructing NAND-NAND logic, in place of AND-OR logic is as follows:
² Produce a reduced Sum-Of-Products logic design.
² When drawing the wiring diagram of the SOP, replace all gates (both AND and OR) with
NAND gates.
² Unused inputs should be tied to logic High.
² In case of troubleshooting, internal nodes at the ¯rst level of NAND gate outputs do NOT
match AND-OR diagram logic levels, but are inverted. Use the NAND-NAND logic diagram.
Inputs and ¯nal output are identical, though.
² Label any multiple packages U1, U2,.. etc.
² Use data sheet to assign pin numbers to inputs and outputs of all gates.
258 CHAPTER 8. KARNAUGH MAPPING
Example:
Let us revisit a previous problem involving an SOP minimization. Produce a Product-Of-Sums
solution. Compare the POS solution to the previous SOP.
AB
CD
1
Out= A C + AD + BC + BD
Out= A B C D + A B C D + A B CD
+ A B C D + A B CD + A BCD
+ A B C D + A B CD + ABCD
1
1
1
1
×
1
1 1 1
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10 0 0 0 0
0
0
0
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10 0 0 0 0
0
0
0
Out= (A+B)( C +D)
Solution:
Above left we have the original problem starting with a 9-minterm Boolean unsimpli¯ed ex-
pression. Reviewing, we formed four groups of 4-cells to yield a 4-product-term SOP result, lower
left.
In the middle ¯gure, above, we ¯ll in the empty spaces with the implied 0s. The 0s form two
groups of 4-cells. The solid red group is (A'+B), the dashed red group is (C'+D). This yields two
sum-terms in the Product-Of-Sums result, above right Out = (A'+B)(C'+D)
Comparing the previous SOP simpli¯cation, left, to the POS simpli¯cation, right, shows that
the POS is the least cost solution. The SOP uses 5-gates total, the POS uses only 3-gates. This
POS solution even looks attractive when using TTL logic due to simplicity of the result. We can
¯nd AND gates and an OR gate with 2-inputs.
C
D
A
B
Out
Out= A C + AD + BC + BD Out= (A+B)( C +D)
Out
D
A
B
C
8.8. MINTERM VS MAXTERM SOLUTION 259
The SOP and POS gate diagrams are shown above for our comparison problem.
Given the pin-outs for the TTL logic family integrated circuit gates below, label the maxterm
diagram above right with Circuit designators (U1-a, U1-b, U2-a, etc), and pin numbers.
1 2 3 4 5 6 7
14 13 12 11 10 9 8
7408
GND
VCC
1 2 3 4 5 6 7
14 13 12 11 10 9 8
7432
GND
VCC
1 2 3 4 5 6 7
14 13 12 11 10 9 8
7404
GND
VCC
Out= (A + B) ( C + D )
Out
D
A
B
C
Each integrated circuit package that we use will receive a circuit designator: U1, U2, U3. To
distinguish between the individual gates within the package, they are identi¯ed as a, b, c, d, etc.
The 7404 hex-inverter package is U1. The individual inverters in it are are U1-a, U1-b, U1-c, etc. U2
is assigned to the 7432 quad OR gate. U3 is assigned to the 7408 quad AND gate. With reference
to the pin numbers on the package diagram above, we assign pin numbers to all gate inputs and
outputs on the schematic diagram below.
We can now build this circuit in a laboratory setting. Or, we could design a printed circuit board
for it. A printed circuit board contains copper foil "wiring" backed by a non conductive substrate
of phenolic, or epoxy-¯berglass. Printed circuit boards are used to mass produce electronic circuits.
Ground the inputs of unused gates.
260 CHAPTER 8. KARNAUGH MAPPING
Out= ( A +B) ( C + D )
Out
D
A
B
C
1
2
3
4
5
6
1
2
3
1 2
3 4
U1-a
U1-b
U2-a
U2-b
U3-a
U1 = 7404
U2 = 7432
U3 = 7408
Label the previous POS solution diagram above left (third ¯gure back) with Circuit designators
and pin numbers. This will be similar to what we just did.
1 2 3 4 5 6 7
14 13 12 11 10 9 8
7420
GND
VCC
1 2 3 4 5 6 7
14 13 12 11 10 9 8
7400
GND
VCC
We can ¯nd 2-input AND gates, 7408 in the previous example. However, we have trouble ¯nding
a 4-input OR gate in our TTL catalog. The only kind of gate with 4-inputs is the 7420 NAND gate
shown above right.
We can make the 4-input NAND gate into a 4-input OR gate by inverting the inputs to the NAND
gate as shown below. So we will use the 7420 4-input NAND gate as an OR gate by inverting the
inputs.
Y= A B = A+B DeMorgan’s
Y=A+B Double negation =
We will not use discrete inverters to invert the inputs to the 7420 4-input NAND gate, but will
drive it with 2-input NAND gates in place of the AND gates called for in the SOP, minterm, solution.
The inversion at the output of the 2-input NAND gates supply the inversion for the 4-input OR
gate.
8.9. § (SUM) AND ¦ (PRODUCT) NOTATION 261
C
D
A
B
Out
Out= A C + AD + B C + BD
U1-b
U1-a
U2-d
U3-a
U2-c
U2-b
U2-a
1
2
3 4
5
6
2
1
3
4
9 8
10
12 11
13
1
2
4
5
6
U1 = 7404
U2 = 7400
U3 = 7420
Out= ( AC ) ( AD )( B C ) ( BD )
Out= A C + AD + B C + BD
Boolean from diagram
DeMorgan’s
Double negation
The result is shown above. It is the only practical way to actually build it with TTL gates by
using NAND-NAND logic replacing AND-OR logic.
8.9 § (sum) and ¦ (product) notation
For reference, this section introduces the terminology used in some texts to describe the minterms
and maxterms assigned to a Karnaugh map. Otherwise, there is no new material here.
§ (sigma) indicates sum and lower case "m" indicates minterms. §m indicates sum of minterms.
The following example is revisited to illustrate our point. Instead of a Boolean equation description
of unsimpli¯ed logic, we list the minterms.
f(A,B,C,D) = § m(1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 13, 15)
or
f(A,B,C,D) = §(m1,m2,m3,m4,m5,m7,m8,m9,m11,m12,m13,m15)
The numbers indicate cell location, or address, within a Karnaugh map as shown below right.
This is certainly a compact means of describing a list of minterms or cells in a K-map.
262 CHAPTER 8. KARNAUGH MAPPING
AB
CD
1
f(A,B,C,D) = A C + AD + B C + B D
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10
AB
CD
0
00 01 11 10
00
01
11
10 0 0 0 0
0
0
0
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10 0 0 0 0
0
0
0
1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
Out= A B C D + A B C D + A B C D
+ A B C D + A B C D + A B C D
+ A B C D + A B CD + A B C D
f(A,B,C,D)=å m(0,1,3,4,5,7,12,13,15)
The Sum-Of-Products solution is not a®ected by the new terminology. The minterms, 1s, in the
map have been grouped as usual and a Sum-OF-Products solution written.
Below, we show the terminology for describing a list of maxterms. Product is indicated by
the Greek ¦ (pi), and upper case "M" indicates maxterms. ¦M indicates product of maxterms.
The same example illustrates our point. The Boolean equation description of unsimpli¯ed logic, is
replaced by a list of maxterms.
f(A,B,C,D) = ¦ M(2, 6, 8, 9, 10, 11, 14)
or
f(A,B,C,D) = ¦(M2, M6, M8, M9, M10, M11, M14)
Once again, the numbers indicate K-map cell address locations. For maxterms this is the location
of 0s, as shown below. A Product-OF-Sums solution is completed in the usual manner.
8.10. DON'T CARE CELLS IN THE KARNAUGH MAP 263
AB
CD
0
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10 0 0 0 0
0
0
0
f(A,B,C,D)= ( A+B)( C +D)
1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
f(A,B,C,D)= P M(2,6,8,9,10,11,14)
Out= (A+B+C +D)(A +B+ C+D)(A +B+ C+D)( A +B+C+D)
(A+B+C+D)( A+B+C+ D )(A +B+C+D)
AB
CD
1
1
1
1
1
1
1 1 1
00 01 11 10
00
01
11
10 0 0 0 0
0
0
0
8.10 Don't care cells in the Karnaugh map
Up to this point we have considered logic reduction problems where the input conditions were
completely speci¯ed. That is, a 3-variable truth table or Karnaugh map had 2n = 23 or 8-entries, a
full table or map. It is not always necessary to ¯ll in the complete truth table for some real-world
problems. We may have a choice to not ¯ll in the complete table.
For example, when dealing with BCD (Binary Coded Decimal) numbers encoded as four bits, we
may not care about any codes above the BCD range of (0, 1, 2...9). The 4-bit binary codes for the
hexadecimal numbers (Ah, Bh, Ch, Eh, Fh) are not valid BCD codes. Thus, we do not have to ¯ll
in those codes at the end of a truth table, or K-map, if we do not care to. We would not normally
care to ¯ll in those codes because those codes (1010, 1011, 1100, 1101, 1110, 1111) will never exist
as long as we are dealing only with BCD encoded numbers. These six invalid codes are don't cares
as far as we are concerned. That is, we do not care what output our logic circuit produces for these
don't cares.
Don't cares in a Karnaugh map, or truth table, may be either 1s or 0s, as long as we don't
care what the output is for an input condition we never expect to see. We plot these cells with an
asterisk, *, among the normal 1s and 0s. When forming groups of cells, treat the don't care cell as
either a 1 or a 0, or ignore the don't cares. This is helpful if it allows us to form a larger group than
would otherwise be possible without the don't cares. There is no requirement to group all or any of
the don't cares. Only use them in a group if it simpli¯es the logic.
264 CHAPTER 8. KARNAUGH MAPPING
A
BC
0
1
00 01 11 10
* *
0 0 0 0
0 1
Out = AC
A
BC
0
1
00 01 11 10
0 0 0 0
0 1
Out = A B C
A
BC
0
1
00 01 11 10
* *
0 0 0 0
0 1
ABC = 0XX > 1XX > A
ABC = XX0 > XX1 > C
input comp- Sum
Out = A C (POS)
lement term
* *
Above is an example of a logic function where the desired output is 1 for input ABC = 101
over the range from 000 to 101. We do not care what the output is for the other possible inputs
(110, 111). Map those two as don't cares. We show two solutions. The solution on the right Out
= AB'C is the more complex solution since we did not use the don't care cells. The solution in the
middle, Out=AC, is less complex because we grouped a don't care cell with the single 1 to form a
group of two. The third solution, a Product-Of-Sums on the right, results from grouping a don't
care with three zeros forming a group of four 0s. This is the same, less complex, Out=AC. We
have illustrated that the don't care cells may be used as either 1s or 0s, whichever is useful.
A to D L1
L2
L3
L4
L5
generator
tach- lamp logic
ometer
The electronics class of Lightning State College has been asked to build the lamp logic for a
stationary bicycle exhibit at the local science museum. As a rider increases his pedaling speed,
lamps will light on a bar graph display. No lamps will light for no motion. As speed increases, the
lower lamp, L1 lights, then L1 and L2, then, L1, L2, and L3, until all lamps light at the highest
speed. Once all the lamps illuminate, no further increase in speed will have any e®ect on the display.
A small DC generator coupled to the bicycle tire outputs a voltage proportional to speed. It
drives a tachometer board which limits the voltage at the high end of speed where all lamps light.
No further increase in speed can increase the voltage beyond this level. This is crucial because the
downstream A to D (Analog to Digital) converter puts out a 3-bit code, ABC, 23 or 8-codes, but
we only have ¯ve lamps. A is the most signi¯cant bit, C the least signi¯cant bit.
The lamp logic needs to respond to the six codes out of the A to D. For ABC=000, no motion,
no lamps light. For the ¯ve codes (001 to 101) lamps L1, L1&L2, L1&L2&L3, up to all lamps will
light, as speed, voltage, and the A to D code (ABC) increases. We do not care about the response
to input codes (110, 111) because these codes will never come out of the A to D due to the limiting
in the tachometer block. We need to design ¯ve logic circuits to drive the ¯ve lamps.
8.10. DON'T CARE CELLS IN THE KARNAUGH MAP 265
A
BC
0
1
00 01 11 10
L1
A
BC
0
1
00 01 11 10
L2
A
BC
0
1
00 01 11 10
L4
A
BC
0
1
00 01 11 10
L3
A
BC
0
1
00 01 11 10
L5
* * * * * *
* * * *
0 0
0
0
0
1 1
1 1 1 1 1
1 1
0
1 1
0 1 0
1 1
0 0 0 0 0 0
0 1
L1 = A + B + C L2 = A + B L3 = A + BC
L4 = A L5 = AC
Since, none of the lamps light for ABC=000 out of the A to D, enter a 0 in all K-maps for
cell ABC=000. Since we don't care about the never to be encountered codes (110, 111), enter
asterisks into those two cells in all ¯ve K-maps.
Lamp L5 will only light for code ABC=101. Enter a 1 in that cell and ¯ve 0s into the remaining
empty cells of L5 K-map.
L4 will light initially for code ABC=100, and will remain illuminated for any code greater,
ABC=101, because all lamps below L5 will light when L5 lights. Enter 1s into cells 100 and 101
of the L4 map so that it will light for those codes. Four 0's ¯ll the remaining L4 cells
L3 will initially light for code ABC=011. It will also light whenever L5 and L4 illuminate.
Enter three 1s into cells 011, 100, 101 for L3 map. Fill three 0s into the remaining L3 cells.
L2 lights for ABC=010 and codes greater. Fill 1s into cells 010, 011, 100, 101, and two 0s
in the remaining cells.
The only time L1 is not lighted is for no motion. There is already a 0 in cell ABC=000. All
the other ¯ve cells receive 1s.
Group the 1's as shown above, using don't cares whenever a larger group results. The L1 map
shows three product terms, corresponding to three groups of 4-cells. We used both don't cares in
two of the groups and one don't care on the third group. The don't cares allowed us to form groups
of four.
In a similar manner, the L2 and L4 maps both produce groups of 4-cells with the aid of the don't
care cells. The L4 reduction is striking in that the L4 lamp is controlled by the most signi¯cant bit
from the A to D converter, L5=A. No logic gates are required for lamp L4. In the L3 and L5 maps,
single cells form groups of two with don't care cells. In all ¯ve maps, the reduced Boolean equation
is less complex than without the don't cares.
266 CHAPTER 8. KARNAUGH MAPPING
A
C
A
B
+5VDC
AC
A+BC
A+B
A+B+C
L5
L4
L3
L2
L1
5x470W
U1a
U2a
U1b
U3a
U2b
U2c
U3b
U3c
U3d
U3e
7408
7432
7406
The gate diagram for the circuit is above. The outputs of the ¯ve K-map equations drive
inverters. Note that the L1 OR gate is not a 3-input gate but a 2-input gate having inputs (A+B),
C, outputting A+B+C The open collector inverters, 7406, are desirable for driving LEDs, though,
not part of the K-map logic design. The output of an open collecter gate or inverter is open
circuited at the collector internal to the integrated circuit package so that all collector current may
°ow through an external load. An active high into any of the inverters pulls the output low, drawing
current through the LED and the current limiting resistor. The LEDs would likely be part of a solid
state relay driving 120VAC lamps for a museum exhibit, not shown here.
8.11 Larger 5 & 6-variable Karnaugh maps
Larger Karnaugh maps reduce larger logic designs. How large is large enough? That depends on the
number of inputs, fan-ins, to the logic circuit under consideration. One of the large programmable
logic companies has an answer.
Altera's own data, extracted from its library of customer designs, supports the value
of heterogeneity. By examining logic cones, mapping them onto LUT-based nodes and
sorting them by the number of inputs that would be best at each node, Altera found
that the distribution of fan-ins was nearly °at between two and six inputs, with a nice
peak at ¯ve.
The answer is no more than six inputs for most all designs, and ¯ve inputs for the average logic
design. The ¯ve variable Karnaugh map follows.
8.11. LARGER 5 & 6-VARIABLE KARNAUGH MAPS 267
00
01
11
10
AB
CDE
000 001 011 010 110 111 101 100
5- variable Karnaugh map (Gray code)
The older version of the ¯ve variable K-map, a Gray Code map or re°ection map, is shown above.
The top (and side for a 6-variable map) of the map is numbered in full Gray code. The Gray code
re°ects about the middle of the code. This style map is found in older texts. The newer preferred
style is below.
00
01
11
10
AB
CDE
000 001 011 010 100 101 111 110
5- variable Karnaugh map (overlay)
The overlay version of the Karnaugh map, shown above, is simply two (four for a 6-variable map)
identical maps except for the most signi¯cant bit of the 3-bit address across the top. If we look at
the top of the map, we will see that the numbering is di®erent from the previous Gray code map.
If we ignore the most signi¯cant digit of the 3-digit numbers, the sequence 00, 01, 11, 10 is at the
heading of both sub maps of the overlay map. The sequence of eight 3-digit numbers is not Gray
code. Though the sequence of four of the least signi¯cant two bits is.
Let's put our 5-variable Karnaugh Map to use. Design a circuit which has a 5-bit binary input
(A, B, C, D, E), with A being the MSB (Most Signi¯cant Bit). It must produce an output logic
High for any prime number detected in the input data.
268 CHAPTER 8. KARNAUGH MAPPING
00
01
11
10
AB
CDE
000 001 011 010 110 111 101 100
5- variable Karnaugh map (Gray code)
1 1
1 1
1 1
1 1 1
1 1
A BE
BCE ACDE
ABDE ABCE
mirror line
1
A B C D
We show the solution above on the older Gray code (re°ection) map for reference. The prime
numbers are (1,2,3,5,7,11,13,17,19,23,29,31). Plot a 1 in each corresponding cell. Then, proceed
with grouping of the cells. Finish by writing the simpli¯ed result. Note that 4-cell group A'B'E
consists of two pairs of cell on both sides of the mirror line. The same is true of the 2-cell group
AB'DE. It is a group of 2-cells by being re°ected about the mirror line. When using this version of
the K-map look for mirror images in the other half of the map.
Out = A'B'E + B'C'E + A'C'DE + A'CD'E + ABCE + AB'DE + A'B'C'D
Below we show the more common version of the 5-variable map, the overlay map.
AB
CDE
000 001 011 010 100 101 111 110
5- variable Karnaugh map (overlay)
00
01
11
10
1 1 1 1
1 1
1 1 1
1 1
A BE
B CE
ACDE
ABDE
A CDE
ABCE
A B CD
1
If we compare the patterns in the two maps, some of the cells in the right half of the map are
moved around since the addressing across the top of the map is di®erent. We also need to take a
8.11. LARGER 5 & 6-VARIABLE KARNAUGH MAPS 269
di®erent approach at spotting commonality between the two halves of the map. Overlay one half of
the map atop the other half. Any overlap from the top map to the lower map is a potential group.
The ¯gure below shows that group AB'DE is composed of two stacked cells. Group A'B'E consists
of two stacked pairs of cells.
For the A'B'E group of 4-cells ABCDE = 00xx1 for the group. That is A,B,E are the same
001 respectively for the group. And, CD=xx that is it varies, no commonality in CD=xx for the
group of 4-cells. Since ABCDE = 00xx1, the group of 4-cells is covered by A'B'XXE = A'B'E.
000 001 011 010
101 111 110
00
01
11
10
11
10
1 1
1
1 1
1 1
1
1 1
1
A BE
ABDE
1
The above 5-variable overlay map is shown stacked.
An example of a six variable Karnaugh map follows. We have mentally stacked the four sub
maps to see the group of 4-cells corresponding to Out = C'F'
270 CHAPTER 8. KARNAUGH MAPPING
000 001 011
110
000
001
011
010
110
110
010
010
110
1
1
1
1
010
ABC
DEF
Out = CF
A magnitude comparator (used to illustrate a 6-variable K-map) compares two binary numbers,
indicating if they are equal, greater than, or less than each other on three respective outputs. A three
bit magnitude comparator has two inputs A2A1A0 and B2B1B0 An integrated circuit magnitude
comparator (7485) would actually have four inputs, But, the Karnaugh map below needs to be kept
to a reasonable size. We will only solve for the A>B output.
Below, a 6-variable Karnaugh map aids simpli¯cation of the logic for a 3-bit magnitude com-
parator. This is an overlay type of map. The binary address code across the top and down the left
side of the map is not a full 3-bit Gray code. Though the 2-bit address codes of the four sub maps
is Gray code. Find redundant expressions by stacking the four sub maps atop one another (shown
above). There could be cells common to all four maps, though not in the example below. It does
have cells common to pairs of sub maps.
AA=B
A>B
A
B
Magnitude
Comparator
The A>B output above is ABC>XYZ on the map below.
8.11. LARGER 5 & 6-VARIABLE KARNAUGH MAPS 271
6- variable Karnaugh map (overlay)
00
01
11
10
000 001 011 010 100 101 111 110
00
01
11
10
ABC
XYZ
1
1
1
1
0
0
0
0
1
1
1 1
1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1
1 1
1 1
1
AX
B X Y
A B Y A B C Z
B C X Z
C X Y Z
A CY Z
Out = A X + A B Y + B X Y +A BC Z +A C Y Z +B C X Z + C X Y Z
Where ever ABC is greater than XYZ, a 1 is plotted. In the ¯rst line ABC=000 cannot be
greater than any of the values of XYZ. No 1s in this line. In the second line, ABC=001, only the
¯rst cell ABCXYZ= 001000 is ABC greater than XYZ. A single 1 is entered in the ¯rst cell of
the second line. The fourth line, ABC=010, has a pair of 1s. The third line, ABC=011 has three
1s. Thus, the map is ¯lled with 1s in any cells where ABC is greater than XXZ.
In grouping cells, form groups with adjacent sub maps if possible. All but one group of 16-cells
involves cells from pairs of the sub maps. Look for the following groups:
² 1 group of 16-cells
² 2 groups of 8-cells
² 4 groups of 4-cells
The group of 16-cells, AX' occupies all of the lower right sub map; though, we don't circle it on the
¯gure above.
One group of 8-cells is composed of a group of 4-cells in the upper sub map overlaying a similar
group in the lower left map. The second group of 8-cells is composed of a similar group of 4-cells in
the right sub map overlaying the same group of 4-cells in the lower left map.
The four groups of 4-cells are shown on the Karnaugh map above with the associated product
terms. Along with the product terms for the two groups of 8-cells and the group of 16-cells, the ¯nal
Sum-Of-Products reduction is shown, all seven terms. Counting the 1s in the map, there is a total
272 CHAPTER 8. KARNAUGH MAPPING
of 16+6+6=28 ones. Before the K-map logic reduction there would have been 28 product terms in
our SOP output, each with 6-inputs. The Karnaugh map yielded seven product terms of four or less
inputs. This is really what Karnaugh maps are all about!
The wiring diagram is not shown. However, here is the parts list for the 3-bit magnitude com-
parator for ABC>XYZ using 4 TTL logic family parts:
² 1 ea 7410 triple 3-input NAND gate AX', ABY', BX'Y'
² 2 ea 7420 dual 4-input NAND gate ABCZ', ACY'Z', BCX'Z', CX'Y'Z'
² 1 ea 7430 8-input NAND gate for output of 7-P-terms
² REVIEW:
² Boolean algebra, Karnaugh maps, and CAD (Computer Aided Design) are methods of logic
simpli¯cation. The goal of logic simpli¯cation is a minimal cost solution.
² A minimal cost solution is a valid logic reduction with the minimum number of gates with the
minimum number of inputs.
² Venn diagrams allow us to visualize Boolean expressions, easing the transition to Karnaugh
maps.
² Karnaugh map cells are organized in Gray code order so that we may visualize redundancy in
Boolean expressions which results in simpli¯cation.
² The more common Sum-Of-Products (Sum of Minters) expressions are implemented as AND
gates (products) feeding a single OR gate (sum).
² Sum-Of-Products expressions (AND-OR logic) are equivalent to a NAND-NAND implemen-
tation. All AND gates and OR gates are replaced by NAND gates.
² Less often used, Product-Of-Sums expressions are implemented as OR gates (sums) feeding into
a single AND gate (product). Product-Of-Sums expressions are based on the 0s, maxterms,
in a Karnaugh map.
Chapter 9
COMBINATIONAL LOGIC
FUNCTIONS
Contents
*** PENDING ***
273
274 CHAPTER 9. COMBINATIONAL LOGIC FUNCTIONS
Chapter 10
MULTIVIBRATORS
Contents
10.1 Digital logic with feedback . . . . . . . . . . . . . . . . . . . . . . . . . . 275
10.2 The S-R latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
10.3 The gated S-R latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
10.4 The D latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
10.5 Edge-triggered latches: Flip-Flops . . . . . . . . . . . . . . . . . . . . . 286
10.6 The J-K °ip-°op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.7 Asynchronous °ip-°op inputs . . . . . . . . . . . . . . . . . . . . . . . . 293
10.8 Monostable multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . 295
10.1 Digital logic with feedback
With simple gate and combinational logic circuits, there is a de¯nite output state for any given input
state. Take the truth table of an OR gate, for instance:
275
276 CHAPTER 10. MULTIVIBRATORS
L1 L2
A
B
A B Output
0 0
0 1
1 0
1 1
0
1
1
1
A
B
Output
Output
For each of the four possible combinations of input states (0-0, 0-1, 1-0, and 1-1), there is one,
de¯nite, unambiguous output state. Whether we're dealing with a multitude of cascaded gates or a
single gate, that output state is determined by the truth table(s) for the gate(s) in the circuit, and
nothing else.
However, if we alter this gate circuit so as to give signal feedback from the output to one of the
inputs, strange things begin to happen:
10.1. DIGITAL LOGIC WITH FEEDBACK 277
L1 L2
A
A
Output
Output
A
0
1
Output
?
1
CR1
CR1
We know that if A is 1, the output must be 1, as well. Such is the nature of an OR gate: any
"high" (1) input forces the output "high" (1). If A is "low" (0), however, we cannot guarantee the
logic level or state of the output in our truth table. Since the output feeds back to one of the OR
gate's inputs, and we know that any 1 input to an OR gates makes the output 1, this circuit will
"latch" in the 1 output state after any time that A is 1. When A is 0, the output could be either
0 or 1, depending on the circuit's prior state! The proper way to complete the above truth table
would be to insert the word latch in place of the question mark, showing that the output maintains
its last state when A is 0.
Any digital circuit employing feedback is called a multivibrator. The example we just explored
with the OR gate was a very simple example of what is called a bistable multivibrator. It is
called "bistable" because it can hold stable in one of two possible output states, either 0 or 1.
There are also monostable multivibrators, which have only one stable output state (that other state
being momentary), which we'll explore later; and astable multivibrators, which have no stable state
(oscillating back and forth between an output of 0 and 1).
A very simple astable multivibrator is an inverter with the output fed directly back to the input:
278 CHAPTER 10. MULTIVIBRATORS
L1 L2
Output
CR1 CR1
Inverter with feedback
When the input is 0, the output switches to 1. That 1 output gets fed back to the input as a 1.
When the input is 1, the output switches to 0. That 0 output gets fed back to the input as a 0, and
the cycle repeats itself. The result is a high frequency (several megahertz) oscillator, if implemented
with a solid-state (semiconductor) inverter gate:
If implemented with relay logic, the resulting oscillator will be considerably slower, cycling at
a frequency well within the audio range. The buzzer or vibrator circuit thus formed was used
extensively in early radio circuitry, as a way to convert steady, low-voltage DC power into pulsating
DC power which could then be stepped up in voltage through a transformer to produce the high
voltage necessary for operating the vacuum tube ampli¯ers. Henry Ford's engineers also employed
the buzzer/transformer circuit to create continuous high voltage for operating the spark plugs on
Model T automobile engines:
"Model T" high-voltage
ignition coil
Borrowing terminology from the old mechanical buzzer (vibrator) circuits, solid-state circuit en-
10.2. THE S-R LATCH 279
gineers referred to any circuit with two or more vibrators linked together as a multivibrator. The
astable multivibrator mentioned previously, with only one "vibrator," is more commonly imple-
mented with multiple gates, as we'll see later.
The most interesting and widely used multivibrators are of the bistable variety, so we'll explore
them in detail now.
10.2 The S-R latch
A bistable multivibrator has two stable states, as indicated by the pre¯x bi in its name. Typically,
one state is referred to as set and the other as reset. The simplest bistable device, therefore, is
known as a set-reset, or S-R, latch.
To create an S-R latch, we can wire two NOR gates in such a way that the output of one feeds
back to the input of another, and vice versa, like this:
R
S
Q
Q
S R
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
0 0
The Q and not-Q outputs are supposed to be in opposite states. I say "supposed to" because
making both the S and R inputs equal to 1 results in both Q and not-Q being 0. For this reason,
having both S and R equal to 1 is called an invalid or illegal state for the S-R multivibrator.
Otherwise, making S=1 and R=0 "sets" the multivibrator so that Q=1 and not-Q=0. Conversely,
making R=1 and S=0 "resets" the multivibrator in the opposite state. When S and R are both
equal to 0, the multivibrator's outputs "latch" in their prior states. Note how the same multivibrator
function can be implemented in ladder logic, with the same results:
280 CHAPTER 10. MULTIVIBRATORS
S R
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
0 0
L1 L2
R CR1
CR2
S CR2
CR1
CR1
CR2
Q
Q
By de¯nition, a condition of Q=1 and not-Q=0 is set. A condition of Q=0 and not-Q=1 is reset.
These terms are universal in describing the output states of any multivibrator circuit.
The astute observer will note that the initial power-up condition of either the gate or ladder
variety of S-R latch is such that both gates (coils) start in the de-energized mode. As such, one
would expect that the circuit will start up in an invalid condition, with both Q and not-Q outputs
being in the same state. Actually, this is true! However, the invalid condition is unstable with both
S and R inputs inactive, and the circuit will quickly stabilize in either the set or reset condition
because one gate (or relay) is bound to react a little faster than the other. If both gates (or coils)
were precisely identical, they would oscillate between high and low like an astable multivibrator upon
power-up without ever reaching a point of stability! Fortunately for cases like this, such a precise
match of components is a rare possibility.
It must be noted that although an astable (continually oscillating) condition would be extremely
rare, there will most likely be a cycle or two of oscillation in the above circuit, and the ¯nal state of
the circuit (set or reset) after power-up would be unpredictable. The root of the problem is a race
condition between the two relays CR1 and CR2.
A race condition occurs when two mutually-exclusive events are simultaneously initiated through
di®erent circuit elements by a single cause. In this case, the circuit elements are relays CR1 and CR2,
and their de-energized states are mutually exclusive due to the normally-closed interlocking contacts.
If one relay coil is de-energized, its normally-closed contact will keep the other coil energized, thus
maintaining the circuit in one of two states (set or reset). Interlocking prevents both relays from
latching. However, if both relay coils start in their de-energized states (such as after the whole circuit
has been de-energized and is then powered up) both relays will "race" to become latched on as they
receive power (the "single cause") through the normally-closed contact of the other relay. One of
those relays will inevitably reach that condition before the other, thus opening its normally-closed
interlocking contact and de-energizing the other relay coil. Which relay "wins" this race is dependent
on the physical characteristics of the relays and not the circuit design, so the designer cannot ensure
10.2. THE S-R LATCH 281
which state the circuit will fall into after power-up.
Race conditions should be avoided in circuit design primarily for the unpredictability that will
be created. One way to avoid such a condition is to insert a time-delay relay into the circuit to
disable one of the competing relays for a short time, giving the other one a clear advantage. In
other words, by purposely slowing down the de-energization of one relay, we ensure that the other
relay will always "win" and the race results will always be predictable. Here is an example of how
a time-delay relay might be applied to the above circuit to avoid the race condition:
L1 L2
R CR1
CR2
S CR2
CR1
CR1
CR2
Q
Q
TD1
TD1
1 second
When the circuit powers up, time-delay relay contact TD1 in the ¯fth rung down will delay closing
for 1 second. Having that contact open for 1 second prevents relay CR2 from energizing through
contact CR1 in its normally-closed state after power-up. Therefore, relay CR1 will be allowed to
energize ¯rst (with a 1-second head start), thus opening the normally-closed CR1 contact in the ¯fth
rung, preventing CR2 from being energized without the S input going active. The end result is that
the circuit powers up cleanly and predictably in the reset state with S=0 and R=0.
It should be mentioned that race conditions are not restricted to relay circuits. Solid-state logic
gate circuits may also su®er from the ill e®ects of race conditions if improperly designed. Complex
computer programs, for that matter, may also incur race problems if improperly designed. Race
problems are a possibility for any sequential system, and may not be discovered until some time
after initial testing of the system. They can be very di±cult problems to detect and eliminate.
A practical application of an S-R latch circuit might be for starting and stopping a motor, using
normally-open, momentary pushbutton switch contacts for both start (S) and stop (R) switches,
then energizing a motor contactor with either a CR1 or CR2 contact (or using a contactor in place
of CR1 or CR2). Normally, a much simpler ladder logic circuit is employed, such as this:
282 CHAPTER 10. MULTIVIBRATORS
L1 L2
CR1
CR1
Start Stop
CR1
Motor "on"
In the above motor start/stop circuit, the CR1 contact in parallel with the start switch contact
is referred to as a "seal-in" contact, because it "seals" or latches control relay CR1 in the energized
state after the start switch has been released. To break the "seal," or to "unlatch" or "reset" the
circuit, the stop pushbutton is pressed, which de-energizes CR1 and restores the seal-in contact to its
normally open status. Notice, however, that this circuit performs much the same function as the S-R
latch. Also note that this circuit has no inherent instability problem (if even a remote possibility)
as does the double-relay S-R latch design.
In semiconductor form, S-R latches come in prepackaged units so that you don't have to build
them from individual gates. They are symbolized as such:
S Q
R Q
² REVIEW:
² A bistable multivibrator is one with two stable output states.
² In a bistable multivibrator, the condition of Q=1 and not-Q=0 is de¯ned as set. A condition
of Q=0 and not-Q=1 is conversely de¯ned as reset. If Q and not-Q happen to be forced to the
same state (both 0 or both 1), that state is referred to as invalid.
² In an S-R latch, activation of the S input sets the circuit, while activation of the R input
resets the circuit. If both S and R inputs are activated simultaneously, the circuit will be in
an invalid condition.
² A race condition is a state in a sequential system where two mutually-exclusive events are
simultaneously initiated by a single cause.
10.3. THE GATED S-R LATCH 283
10.3 The gated S-R latch
It is sometimes useful in logic circuits to have a multivibrator which changes state only when certain
conditions are met, regardless of its S and R input states. The conditional input is called the enable,
and is symbolized by the letter E. Study the following example to see how this works:
R
S
Q
Q
S R
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
0 0
latch latch
latch latch
latch latch
0 0 latch latch
0 1
1 0
1 1
E
0
0
0
0
1
1
1
1
E
When the E=0, the outputs of the two AND gates are forced to 0, regardless of the states of
either S or R. Consequently, the circuit behaves as though S and R were both 0, latching the Q
and not-Q outputs in their last states. Only when the enable input is activated (1) will the latch
respond to the S and R inputs. Note the identical function in ladder logic:
S R
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
0 0
latch latch
latch latch
latch latch
0 0 latch latch
0 1
1 0
1 1
E
0
0
0
0
1
1
1
1
L1 L2
R CR1
CR2
S CR2
CR1
CR1
CR2
Q
Q
E
E
A practical application of this might be the same motor control circuit (with two normally-open
pushbutton switches for start and stop), except with the addition of a master lockout input (E) that
disables both pushbuttons from having control over the motor when it's low (0).
Once again, these multivibrator circuits are available as prepackaged semiconductor devices, and
are symbolized as such:
284 CHAPTER 10. MULTIVIBRATORS
S Q
R Q
E
It is also common to see the enable input designated by the letters "EN" instead of just "E."
² REVIEW:
² The enable input on a multivibrator must be activated for either S or R inputs to have any
e®ect on the output state.
² This enable input is sometimes labeled "E", and other times as "EN".
10.4 The D latch
Since the enable input on a gated S-R latch provides a way to latch the Q and not-Q outputs without
regard to the status of S or R, we can eliminate one of those inputs to create a multivibrator latch
circuit with no "illegal" input states. Such a circuit is called a D latch, and its internal logic looks
like this:
Q
Q
Q Q
latch latch
0 0 latch latch
0 1
1 0
1 1
E
D
E D
0
1 0
1
Note that the R input has been replaced with the complement (inversion) of the old S input,
and the S input has been renamed to D. As with the gated S-R latch, the D latch will not respond
to a signal input if the enable input is 0 { it simply stays latched in its last state. When the enable
input is 1, however, the Q output follows the D input.
Since the R input of the S-R circuitry has been done away with, this latch has no "invalid" or
"illegal" state. Q and not-Q are always opposite of one another. If the above diagram is confusing
at all, the next diagram should make the concept simpler:
S Q
R Q
E
D
E
10.4. THE D LATCH 285
Like both the S-R and gated S-R latches, the D latch circuit may be found as its own prepackaged
circuit, complete with a standard symbol:
Q
D Q
E
The D latch is nothing more than a gated S-R latch with an inverter added to make R the
complement (inverse) of S. Let's explore the ladder logic equivalent of a D latch, modi¯ed from the
basic ladder diagram of an S-R latch:
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
L1 L2
CR1
CR2
CR2
CR1
CR1
CR2
Q
Q
E D
latch latch
1 0
D
D E
E
An application for the D latch is a 1-bit memory circuit. You can "write" (store) a 0 or 1 bit
in this latch circuit by making the enable input high (1) and setting D to whatever you want the
stored bit to be. When the enable input is made low (0), the latch ignores the status of the D input
and merrily holds the stored bit value, outputting at the stored value at Q, and its inverse on output
not-Q.
² REVIEW:
² A D latch is like an S-R latch with only one input: the "D" input. Activating the D input
sets the circuit, and de-activating the D input resets the circuit. Of course, this is only if the
enable input (E) is activated as well. Otherwise, the output(s) will be latched, unresponsive
to the state of the D input.
286 CHAPTER 10. MULTIVIBRATORS
² D latches can be used as 1-bit memory circuits, storing either a "high" or a "low" state when
disabled, and "reading" new data from the D input when enabled.
10.5 Edge-triggered latches: Flip-Flops
So far, we've studied both S-R and D latch circuits with an enable inputs. The latch responds to
the data inputs (S-R or D) only when the enable input is activated. In many digital applications,
however, it is desirable to limit the responsiveness of a latch circuit to a very short period of
time instead of the entire duration that the enabling input is activated. One method of enabling
a multivibrator circuit is called edge triggering, where the circuit's data inputs have control only
during the time that the enable input is transitioning from one state to another. Let's compare
timing diagrams for a normal D latch versus one that is edge-triggered:
D
E
Q
Q
Outputs respond to input (D)
Regular D-latch response
during these time periods
10.5. EDGE-TRIGGERED LATCHES: FLIP-FLOPS 287
D
E
Q
Q
Outputs respond to input (D)
Positive edge-triggered D-latch response
only when enable signal transitions
from low to high
In the ¯rst timing diagram, the outputs respond to input D whenever the enable (E) input is
high, for however long it remains high. When the enable signal falls back to a low state, the circuit
remains latched. In the second timing diagram, we note a distinctly di®erent response in the circuit
output(s): it only responds to the D input during that brief moment of time when the enable signal
changes, or transitions, from low to high. This is known as positive edge-triggering.
There is such a thing as negative edge triggering as well, and it produces the following response
to the same input signals:
D
E
Q
Q
Outputs respond to input (D)
only when enable signal transitions
Negative edge-triggered D-latch response
from high to low
Whenever we enable a multivibrator circuit on the transitional edge of a square-wave enable
signal, we call it a °ip-°op instead of a latch. Consequently, and edge-triggered S-R circuit is more
properly known as an S-R °ip-°op, and an edge-triggered D circuit as a D °ip-°op. The enable
signal is renamed to be the clock signal. Also, we refer to the data inputs (S, R, and D, respectively)
of these °ip-°ops as synchronous inputs, because they have e®ect only at the time of the clock pulse
288 CHAPTER 10. MULTIVIBRATORS
edge (transition), thereby synchronizing any output changes with that clock pulse, rather than at
the whim of the data inputs.
But, how do we actually accomplish this edge-triggering? To create a "gated" S-R latch from a
regular S-R latch is easy enough with a couple of AND gates, but how do we implement logic that
only pays attention to the rising or falling edge of a changing digital signal? What we need is a
digital circuit that outputs a brief pulse whenever the input is activated for an arbitrary period of
time, and we can use the output of this circuit to brie°y enable the latch. We're getting a little
ahead of ourselves here, but this is actually a kind of monostable multivibrator, which for now we'll
call a pulse detector.
Pulse detector
circuit
Output
Input
Input
Output
The duration of each output pulse is set by components in the pulse circuit itself. In ladder logic,
this can be accomplished quite easily through the use of a time-delay relay with a very short delay
time:
L1 L2
Input TD1
TD1 Input
Output
Implementing this timing function with semiconductor components is actually quite easy, as it
exploits the inherent time delay within every logic gate (known as propagation delay). What we do
is take an input signal and split it up two ways, then place a gate or a series of gates in one of those
signal paths just to delay it a bit, then have both the original signal and its delayed counterpart
enter into a two-input gate that outputs a high signal for the brief moment of time that the delayed
signal has not yet caught up to the low-to-high change in the non-delayed signal. An example circuit
for producing a clock pulse on a low-to-high input signal transition is shown here:
10.5. EDGE-TRIGGERED LATCHES: FLIP-FLOPS 289
Input
Output
Input
Delayed input
Delayed input
Output
Brief period of time when
are high
both inputs of the AND gate
This circuit may be converted into a negative-edge pulse detector circuit with only a change of
the ¯nal gate from AND to NOR:
Input
Output
Input
Delayed input
Delayed input
Output
Brief period of time when
are low
both inputs of the NOR gate
Now that we know how a pulse detector can be made, we can show it attached to the enable
input of a latch to turn it into a °ip-°op. In this case, the circuit is a S-R °ip-°op:
R
S
Q
Q
S R
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
0 0
latch latch
latch latch
latch latch
0 0 latch latch
0 1
1 0
1 1
Pulse
detector
C
C
x
x
x
x
Only when the clock signal (C) is transitioning from low to high is the circuit responsive to the
290 CHAPTER 10. MULTIVIBRATORS
S and R inputs. For any other condition of the clock signal ("x") the circuit will be latched.
A ladder logic version of the S-R °ip-°op is shown here:
C TD1
C CR3
S R
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
0 0
latch latch
latch latch
latch latch
0 0 latch latch
0 1
1 0
1 1
L1 L2
R CR1
CR2
S CR2
CR1
CR1
CR2
Q
Q
CR3
CR3
x
x
x
x
TD1
C
Relay contact CR3 in the ladder diagram takes the place of the old E contact in the S-R latch
circuit, and is closed only during the short time that both C is closed and time-delay contact TR1 is
closed. In either case (gate or ladder circuit), we see that the inputs S and R have no e®ect unless
C is transitioning from a low (0) to a high (1) state. Otherwise, the °ip-°op's outputs latch in their
previous states.
It is important to note that the invalid state for the S-R °ip-°op is maintained only for the
short period of time that the pulse detector circuit allows the latch to be enabled. After that brief
time period has elapsed, the outputs will latch into either the set or the reset state. Once again,
the problem of a race condition manifests itself. With no enable signal, an invalid output state
cannot be maintained. However, the valid "latched" states of the multivibrator { set and reset { are
mutually exclusive to one another. Therefore, the two gates of the multivibrator circuit will "race"
each other for supremacy, and whichever one attains a high output state ¯rst will "win."
The block symbols for °ip-°ops are slightly di®erent from that of their respective latch counter-
parts:
10.6. THE J-K FLIP-FLOP 291
S Q
R Q
C
D
C
Q
Q
The triangle symbol next to the clock inputs tells us that these are edge-triggered devices,
and consequently that these are °ip-°ops rather than latches. The symbols above are positive
edge-triggered: that is, they "clock" on the rising edge (low-to-high transition) of the clock signal.
Negative edge-triggered devices are symbolized with a bubble on the clock input line:
S
C
R
Q
Q
D
C
Q
Q
Both of the above °ip-°ops will "clock" on the falling edge (high-to-low transition) of the clock
signal.
² REVIEW:
² A °ip-°op is a latch circuit with a "pulse detector" circuit connected to the enable (E) input,
so that it is enabled only for a brief moment on either the rising or falling edge of a clock pulse.
² Pulse detector circuits may be made from time-delay relays for ladder logic applications, or
from semiconductor gates (exploiting the phenomenon of propagation delay).
10.6 The J-K °ip-°op
Another variation on a theme of bistable multivibrators is the J-K °ip-°op. Essentially, this is a
modi¯ed version of an S-R °ip-°op with no "invalid" or "illegal" output state. Look closely at the
following diagram to see how this is accomplished:
Q
Q
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
latch latch
latch latch
latch latch
0 0 latch latch
0 1
1 0
1 1
Pulse
detector
C
C
x
x
x
x
K
J
J K
toggle toggle
292 CHAPTER 10. MULTIVIBRATORS
What used to be the S and R inputs are now called the J and K inputs, respectively. The old
two-input AND gates have been replaced with 3-input AND gates, and the third input of each gate
receives feedback from the Q and not-Q outputs. What this does for us is permit the J input to have
e®ect only when the circuit is reset, and permit the K input to have e®ect only when the circuit is
set. In other words, the two inputs are interlocked, to use a relay logic term, so that they cannot
both be activated simultaneously. If the circuit is "set," the J input is inhibited by the 0 status of
not-Q through the lower AND gate; if the circuit is "reset," the K input is inhibited by the 0 status
of Q through the upper AND gate.
When both J and K inputs are 1, however, something unique happens. Because of the selective
inhibiting action of those 3-input AND gates, a "set" state inhibits input J so that the °ip-°op acts
as if J=0 while K=1 when in fact both are 1. On the next clock pulse, the outputs will switch
("toggle") from set (Q=1 and not-Q=0) to reset (Q=0 and not-Q=1). Conversely, a "reset" state
inhibits input K so that the °ip-°op acts as if J=1 and K=0 when in fact both are 1. The next
clock pulse toggles the circuit again from reset to set.
See if you can follow this logical sequence with the ladder logic equivalent of the J-K °ip-°op:
C TD1
C CR3
0 0
0
0
1
1
1 1
latch latch
Q Q
0 1
1 0
latch latch
latch latch
latch latch
0 0 latch latch
0 1
1 0
1 1
L1 L2
CR1
CR2
CR2
CR1
CR1
CR2
Q
Q
CR3
CR3
x
x
x
x
TD1
J
K
CR2
CR1
J K
toggle toggle
C
The end result is that the S-R °ip-°op's "invalid" state is eliminated (along with the race con-
dition it engendered) and we get a useful feature as a bonus: the ability to toggle between the two
(bistable) output states with every transition of the clock input signal.
There is no such thing as a J-K latch, only J-K °ip-°ops. Without the edge-triggering of the clock
input, the circuit would continuously toggle between its two output states when both J and K were
10.7. ASYNCHRONOUS FLIP-FLOP INPUTS 293
held high (1), making it an astable device instead of a bistable device in that circumstance. If we
want to preserve bistable operation for all combinations of input states, we must use edge-triggering
so that it toggles only when we tell it to, one step (clock pulse) at a time.
The block symbol for a J-K °ip-°op is a whole lot less frightening than its internal circuitry, and
just like the S-R and D °ip-°ops, J-K °ip-°ops come in two clock varieties (negative and positive
edge-triggered):
J Q
Q
C
K
J
C
K Q
Q
² REVIEW:
² A J-K °ip-°op is nothing more than an S-R °ip-°op with an added layer of feedback. This
feedback selectively enables one of the two set/reset inputs so that they cannot both carry an
active signal to the multivibrator circuit, thus eliminating the invalid condition.
² When both J and K inputs are activated, and the clock input is pulsed, the outputs (Q and
not-Q) will swap states. That is, the circuit will toggle from a set state to a reset state, or vice
versa.
10.7 Asynchronous °ip-°op inputs
The normal data inputs to a °ip °op (D, S and R, or J and K) are referred to as synchronous inputs
because they have e®ect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal
transitions. These extra inputs that I now bring to your attention are called asynchronous because
they can set or reset the °ip-°op regardless of the status of the clock signal. Typically, they're called
preset and clear:
S Q
R Q
C
D
C
Q
Q J Q
Q
C
K
PRE
CLR
PRE
CLR
PRE
CLR
294 CHAPTER 10. MULTIVIBRATORS
When the preset input is activated, the °ip-°op will be set (Q=1, not-Q=0) regardless of any of
the synchronous inputs or the clock. When the clear input is activated, the °ip-°op will be reset
(Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both
preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output,
where Q and not-Q go to the same state, the same as our old friend, the S-R latch! Preset and clear
inputs ¯nd use when multiple °ip-°ops are ganged together to perform a function on a multi-bit
binary word, and a single line is needed to set or reset them all at once.
Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-
low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol,
just like the negative edge-trigger clock inputs.
S Q
R Q
C
D
C
Q
Q J Q
Q
C
K
PRE
CLR
PRE
CLR
PRE
CLR
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them,
to further denote the negative logic of these inputs:
S Q
R Q
C
D
C
Q
Q J Q
Q
C
K
PRE
CLR
PRE
CLR
PRE
CLR
² REVIEW:
² Asynchronous inputs on a °ip-°op have control over the outputs (Q and not-Q) regardless of
clock input status.
² These inputs are called the preset (PRE) and clear (CLR). The preset input drives the °ip-°op
to a set state while the clear input drives it to a reset state.
10.8. MONOSTABLE MULTIVIBRATORS 295
² It is possible to drive the outputs of a J-K °ip-°op to an invalid condition using the asyn-
chronous inputs, because all feedback within the multivibrator circuit is overridden.
10.8 Monostable multivibrators
We've already seen one example of a monostable multivibrator in use: the pulse detector used within
the circuitry of °ip-°ops, to enable the latch portion for a brief time when the clock input signal
transitions from either low to high or high to low. The pulse detector is classi¯ed as a monostable
multivibrator because it has only one stable state. By stable, I mean a state of output where the
device is able to latch or hold to forever, without external prodding. A latch or °ip-°op, being a
bistable device, can hold in either the "set" or "reset" state for an inde¯nite period of time. Once it's
set or reset, it will continue to latch in that state unless prompted to change by an external input.
A monostable device, on the other hand, is only able to hold in one particular state inde¯nitely. Its
other state can only be held momentarily when triggered by an external input.
A mechanical analogy of a monostable device would be a momentary contact pushbutton switch,
which spring-returns to its normal (stable) position when pressure is removed from its button actu-
ator. Likewise, a standard wall (toggle) switch, such as the type used to turn lights on and o® in a
house, is a bistable device. It can latch in one of two modes: on or o®.
All monostable multivibrators are timed devices. That is, their unstable output state will hold
only for a certain minimum amount of time before returning to its stable state. With semiconductor
monostable circuits, this timing function is typically accomplished through the use of resistors and
capacitors, making use of the exponential charging rates of RC circuits. A comparator is often
used to compare the voltage across the charging (or discharging) capacitor with a steady reference
voltage, and the on/o® output of the comparator used for a logic signal. With ladder logic, time
delays are accomplished with time-delay relays, which can be constructed with semiconductor/RC
circuits like that just mentioned, or mechanical delay devices which impede the immediate motion
of the relay's armature. Note the design and operation of the pulse detector circuit in ladder logic:
L1 L2
Input TD1
TD1 Input
Output
Input
Output
1 second
1 second
No matter how long the input signal stays high (1), the output remains high for just 1 second of
time, then returns to its normal (stable) low state.
296 CHAPTER 10. MULTIVIBRATORS
For some applications, it is necessary to have a monostable device that outputs a longer pulse
than the input pulse which triggers it. Consider the following ladder logic circuit:
L1 L2
Input TD1
TD1
Output
Input
Output
10 seconds
10 seconds
10 seconds 10 seconds
When the input contact closes, TD1 contact immediately closes, and stays closed for 10 seconds
after the input contact opens. No matter how short the input pulse is, the output stays high (1)
for exactly 10 seconds after the input drops low again. This kind of monostable multivibrator is
called a one-shot. More speci¯cally, it is a retriggerable one-shot, because the timing begins after
the input drops to a low state, meaning that multiple input pulses within 10 seconds of each other
will maintain a continuous high output:
Input
Output
10 seconds
"Retriggering" action
One application for a retriggerable one-shot is that of a single mechanical contact debouncer.
As you can see from the above timing diagram, the output will remain high despite "bouncing" of
the input signal from a mechanical switch. Of course, in a real-life switch debouncer circuit, you'd
probably want to use a time delay of much shorter duration than 10 seconds, as you only need to
"debounce" pulses that are in the millisecond range.
10.8. MONOSTABLE MULTIVIBRATORS 297
+V
Rpulldown
One-shot
"Dirty" signal
"Clean" signal
Switch
actuated
momentarily
What if we only wanted a 10 second timed pulse output from a relay logic circuit, regardless
of how many input pulses we received or how long-lived they may be? In that case, we'd have to
couple a pulse-detector circuit to the retriggerable one-shot time delay circuit, like this:
L1 L2
Input
TD1
Output
Input
Output
10 seconds
Input
TD2
TD2
0.5 second
TD1 TD2
10 sec. 10 sec. 10 sec.
Time delay relay TD1 provides an "on" pulse to time delay relay coil TD2 for an arbitrarily
short moment (in this circuit, for at least 0.5 second each time the input contact is actuated). As
soon as TD2 is energized, the normally-closed, timed-closed TD2 contact in series with it prevents
coil TD2 from being re-energized as long as it's timing out (10 seconds). This e®ectively makes it
unresponsive to any more actuations of the input switch during that 10 second period.
Only after TD2 times out does the normally-closed, timed-closed TD2 contact in series with it
allow coil TD2 to be energized again. This type of one-shot is called a nonretriggerable one-shot.
One-shot multivibrators of both the retriggerable and nonretriggerable variety ¯nd wide appli-
298 CHAPTER 10. MULTIVIBRATORS
cation in industry for siren actuation and machine sequencing, where an intermittent input signal
produces an output signal of a set time.
² REVIEW:
² A monostable multivibrator has only one stable output state. The other output state can only
be maintained temporarily.
² Monostable multivibrators, sometimes called one-shots, come in two basic varieties: retrigger-
able and nonretriggerable.
² One-shot circuits with very short time settings may be used to debounce the "dirty" signals
created by mechanical switch contacts.
Chapter 11
COUNTERS
Contents
11.1 Binary count sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
11.2 Asynchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
11.3 Synchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
11.4 Counter modulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
*** INCOMPLETE ***
11.1 Binary count sequence
If we examine a four-bit binary count sequence from 0000 to 1111, a de¯nite pattern will be evident
in the "oscillations" of the bits between 0 and 1:
299
300 CHAPTER 11. COUNTERS
0 0 0 0
0 0 0 1
0 0
0 0
1 0
1 1
1
1
1
1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0
0
1 0
1 1
1
1
1
1
0 0
0 1
1 0
1 1
Note how the least signi¯cant bit (LSB) toggles between 0 and 1 for every step in the count
sequence, while each succeeding bit toggles at one-half the frequency of the one before it. The
most signi¯cant bit (MSB) only toggles once during the entire sixteen-step count sequence: at the
transition between 7 (0111) and 8 (1000).
If we wanted to design a digital circuit to "count" in four-bit binary, all we would have to do
is design a series of frequency divider circuits, each circuit dividing the frequency of a square-wave
pulse by a factor of 2:
(LSB)
(MSB)
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
J-K °ip-°ops are ideally suited for this task, because they have the ability to "toggle" their
output state at the command of a clock pulse when both J and K inputs are made "high" (1):
11.2. ASYNCHRONOUS COUNTERS 301
J Q
Q
C
K
Vdd
signal A
signal B
A
B
0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 1 1 0 0 1 1 0
If we consider the two signals (A and B) in this circuit to represent two bits of a binary number,
signal A being the LSB and signal B being the MSB, we see that the count sequence is backward:
from 11 to 10 to 01 to 00 and back again to 11. Although it might not be counting in the direction
we might have assumed, at least it counts!
The following sections explore di®erent types of counter circuits, all made with J-K °ip-°ops,
and all based on the exploitation of that °ip-°op's toggle mode of operation.
² REVIEW:
² Binary count sequences follow a pattern of octave frequency division: the frequency of oscilla-
tion for each bit, from LSB to MSB, follows a divide-by-two pattern. In other words, the LSB
will oscillate at the highest frequency, followed by the next bit at one-half the LSB's frequency,
and the next bit at one-half the frequency of the bit before it, etc.
² Circuits may be built that "count" in a binary sequence, using J-K °ip-°ops set up in the
"toggle" mode.
11.2 Asynchronous counters
In the previous section, we saw a circuit using one J-K °ip-°op that counted backward in a two-bit
binary sequence, from 11 to 10 to 01 to 00. Since it would be desirable to have a circuit that could
count forward and not just backward, it would be worthwhile to examine a forward count sequence
again and look for more patterns that might indicate how to build such a circuit.
Since we know that binary count sequences follow a pattern of octave (factor of 2) frequency
division, and that J-K °ip-°op multivibrators set up for the "toggle" mode are capable of performing
this type of frequency division, we can envision a circuit made up of several J-K °ip-°ops, cascaded
to produce four bits of output. The main problem facing us is to determine how to connect these
°ip-°ops together so that they toggle at the right times to produce the proper binary sequence.
302 CHAPTER 11. COUNTERS
Examine the following binary count sequence, paying attention to patterns preceding the "toggling"
of a bit between 0 and 1:
0 0 0 0
0 0 0 1
0 0
0 0
1 0
1 1
1
1
1
1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0
0
1 0
1 1
1
1
1
1
0 0
0 1
1 0
1 1
Note that each bit in this four-bit sequence toggles when the bit before it (the bit having a lesser
signi¯cance, or place-weight), toggles in a particular direction: from 1 to 0. Small arrows indicate
those points in the sequence where a bit toggles, the head of the arrow pointing to the previous bit
transitioning from a "high" (1) state to a "low" (0) state:
0 0 0 0
0 0 0 1
0 0
0 0
1 0
1 1
1
1
1
1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0
0
1 0
1 1
1
1
1
1
0 0
0 1
1 0
1 1
Starting with four J-K °ip-°ops connected in such a way to always be in the "toggle" mode, we
need to determine how to connect the clock inputs in such a way so that each succeeding bit toggles
11.2. ASYNCHRONOUS COUNTERS 303
when the bit before it transitions from 1 to 0. The Q outputs of each °ip-°op will serve as the
respective binary bits of the ¯nal, four-bit count:
J Q
Q
C
K
Vdd
J Q
Q
C
K
Vdd
?
J Q
Q
C
K
Vdd
?
J Q
Q
C
K
Vdd
?
Q0 Q1 Q2 Q3
If we used °ip-°ops with negative-edge triggering (bubble symbols on the clock inputs), we could
simply connect the clock input of each °ip-°op to the Q output of the °ip-°op before it, so that
when the bit before it changes from a 1 to a 0, the "falling edge" of that signal would "clock" the
next °ip-°op to toggle the next bit:
J Q
Q
C
K
Vdd Vdd Vdd Vdd
Q0 Q1 Q2 Q3
J
C
K Q
Q J
C
K Q
Q J
C
K Q
Q
A four-bit "up" counter
This circuit would yield the following output waveforms, when "clocked" by a repetitive source
of pulses from an oscillator:
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Q0
Q1
Q2
Q3
Clock
The ¯rst °ip-°op (the one with the Q0 output), has a positive-edge triggered clock input, so it
toggles with each rising edge of the clock signal. Notice how the clock signal in this example has a
304 CHAPTER 11. COUNTERS
duty cycle less than 50%. I've shown the signal in this manner for the purpose of demonstrating how
the clock signal need not be symmetrical to obtain reliable, "clean" output bits in our four-bit binary
sequence. In the very ¯rst °ip-°op circuit shown in this chapter, I used the clock signal itself as one
of the output bits. This is a bad practice in counter design, though, because it necessitates the use
of a square wave signal with a 50% duty cycle ("high" time = "low" time) in order to obtain a count
sequence where each and every step pauses for the same amount of time. Using one J-K °ip-°op for
each output bit, however, relieves us of the necessity of having a symmetrical clock signal, allowing
the use of practically any variety of high/low waveform to increment the count sequence.
As indicated by all the other arrows in the pulse diagram, each succeeding output bit is toggled
by the action of the preceding bit transitioning from "high" (1) to "low" (0). This is the pattern
necessary to generate an "up" count sequence.
A less obvious solution for generating an "up" sequence using positive-edge triggered °ip-°ops is
to "clock" each °ip-°op using the Q' output of the preceding °ip-°op rather than the Q output. Since
the Q' output will always be the exact opposite state of the Q output on a J-K °ip-°op (no invalid
states with this type of °ip-°op), a high-to-low transition on the Q output will be accompanied by
a low-to-high transition on the Q' output. In other words, each time the Q output of a °ip-°op
transitions from 1 to 0, the Q' output of the same °ip-°op will transition from 0 to 1, providing
the positive-going clock pulse we would need to toggle a positive-edge triggered °ip-°op at the right
moment:
J Q
Q
C
K
Vdd Vdd Vdd Vdd
Q0 Q1 Q2 Q3
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
A different way of making a four-bit "up" counter
One way we could expand the capabilities of either of these two counter circuits is to regard the
Q' outputs as another set of four binary bits. If we examine the pulse diagram for such a circuit,
we see that the Q' outputs generate a down-counting sequence, while the Q outputs generate an
up-counting sequence:
11.2. ASYNCHRONOUS COUNTERS 305
J Q
Q
C
K
Vdd Vdd Vdd Vdd
Q0 Q1 Q2 Q3
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3
A simultaneous "up" and "down" counter
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Q0
Q1
Q2
Q3
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Q0
Q1
Q2
Q3
"Up" count sequence
"Down" count sequence
Unfortunately, all of the counter circuits shown thusfar share a common problem: the ripple
e®ect. This e®ect is seen in certain types of binary adder and data conversion circuits, and is
due to accumulative propagation delays between cascaded gates. When the Q output of a °ip-°op
transitions from 1 to 0, it commands the next °ip-°op to toggle. If the next °ip-°op toggle is a
transition from 1 to 0, it will command the °ip-°op after it to toggle as well, and so on. However,
since there is always some small amount of propagation delay between the command to toggle (the
clock pulse) and the actual toggle response (Q and Q' outputs changing states), any subsequent °ip-
°ops to be toggled will toggle some time after the ¯rst °ip-°op has toggled. Thus, when multiple
bits toggle in a binary count sequence, they will not all toggle at exactly the same time:
306 CHAPTER 11. COUNTERS
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Q0
Q1
Q2
Q3
Accumulated
delay
Pulse diagram showing (exaggerated) propagation delays
As you can see, the more bits that toggle with a given clock pulse, the more severe the accu-
mulated delay time from LSB to MSB. When a clock pulse occurs at such a transition point (say,
on the transition from 0111 to 1000), the output bits will "ripple" in sequence from LSB to MSB,
as each succeeding bit toggles and commands the next bit to toggle as well, with a small amount
of propagation delay between each bit toggle. If we take a close-up look at this e®ect during the
transition from 0111 to 1000, we can see that there will be false output counts generated in the brief
time period that the "ripple" e®ect takes place:
Q0
Q1
Q2
Q3
1
0
1
1
1
0
0
0 0 0 0
1 0 0
1
0
1
0 0
0
7 8
Count False Count
counts
delay
delay
delay
Instead of cleanly transitioning from a "0111" output to a "1000" output, the counter circuit will
very quickly ripple from 0111 to 0110 to 0100 to 0000 to 1000, or from 7 to 6 to 4 to 0 and then to
8. This behavior earns the counter circuit the name of ripple counter, or asynchronous counter.
11.2. ASYNCHRONOUS COUNTERS 307
In many applications, this e®ect is tolerable, since the ripple happens very, very quickly (the width
of the delays has been exaggerated here as an aid to understanding the e®ects). If all we wanted
to do was drive a set of light-emitting diodes (LEDs) with the counter's outputs, for example, this
brief ripple would be of no consequence at all. However, if we wished to use this counter to drive the
"select" inputs of a multiplexer, index a memory pointer in a microprocessor (computer) circuit, or
perform some other task where false outputs could cause spurious errors, it would not be acceptable.
There is a way to use this type of counter circuit in applications sensitive to false, ripple-generated
outputs, and it involves a principle known as strobing.
Most decoder and multiplexer circuits are equipped with at least one input called the "enable."
The output(s) of such a circuit will be active only when the enable input is made active. We can use
this enable input to strobe the circuit receiving the ripple counter's output so that it is disabled (and
thus not responding to the counter output) during the brief period of time in which the counter
outputs might be rippling, and enabled only when su±cient time has passed since the last clock
pulse that all rippling will have ceased. In most cases, the strobing signal can be the same clock
pulse that drives the counter circuit:
J Q
Q
C
K
Vdd Vdd Vdd Vdd
Q0 Q1 Q2 Q3
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
EN
Binary
count
input
Outputs
Receiving circuit
Counter circuit
Clock signal
With an active-low Enable input, the receiving circuit will respond to the binary count of the
four-bit counter circuit only when the clock signal is "low." As soon as the clock pulse goes "high,"
the receiving circuit stops responding to the counter circuit's output. Since the counter circuit is
positive-edge triggered (as determined by the ¯rst °ip-°op clock input), all the counting action
takes place on the low-to-high transition of the clock signal, meaning that the receiving circuit will
become disabled just before any toggling occurs on the counter circuit's four output bits. The
receiving circuit will not become enabled until the clock signal returns to a low state, which should
be a long enough time after all rippling has ceased to be "safe" to allow the new count to have e®ect
on the receiving circuit. The crucial parameter here is the clock signal's "high" time: it must be at
least as long as the maximum expected ripple period of the counter circuit. If not, the clock signal
will prematurely enable the receiving circuit, while some rippling is still taking place.
Another disadvantage of the asynchronous, or ripple, counter circuit is limited speed. While all
gate circuits are limited in terms of maximum signal frequency, the design of asynchronous counter
circuits compounds this problem by making propagation delays additive. Thus, even if strobing is
used in the receiving circuit, an asynchronous counter circuit cannot be clocked at any frequency
308 CHAPTER 11. COUNTERS
higher than that which allows the greatest possible accumulated propagation delay to elapse well
before the next pulse.
The solution to this problem is a counter circuit that avoids ripple altogether. Such a counter
circuit would eliminate the need to design a "strobing" feature into whatever digital circuits use
the counter output as an input, and would also enjoy a much greater operating speed than its
asynchronous equivalent. This design of counter circuit is the subject of the next section.
² REVIEW:
² An "up" counter may be made by connecting the clock inputs of positive-edge triggered J-K
°ip-°ops to the Q' outputs of the preceding °ip-°ops. Another way is to use negative-edge
triggered °ip-°ops, connecting the clock inputs to the Q outputs of the preceding °ip-°ops. In
either case, the J and K inputs of all °ip-°ops are connected to Vcc or Vdd so as to always be
"high."
² Counter circuits made from cascaded J-K °ip-°ops where each clock input receives its pulses
from the output of the previous °ip-°op invariably exhibit a ripple e®ect, where false output
counts are generated between some steps of the count sequence. These types of counter circuits
are called asynchronous counters, or ripple counters.
² Strobing is a technique applied to circuits receiving the output of an asynchronous (ripple)
counter, so that the false counts generated during the ripple time will have no ill e®ect. Es-
sentially, the enable input of such a circuit is connected to the counter's clock pulse in such a
way that it is enabled only when the counter outputs are not changing, and will be disabled
during those periods of changing counter outputs where ripple occurs.
11.3 Synchronous counters
A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change
state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K
°ip-°ops is to connect all the clock inputs together, so that each and every °ip-°op receives the
exact same clock pulse at the exact same time:
J Q
Q
C
K
J Q
Q
C
K
?
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3
?
?
?
?
?
?
?
Now, the question is, what do we do with the J and K inputs? We know that we still have to
maintain the same divide-by-two frequency pattern in order to count in a binary sequence, and that
this pattern is best achieved utilizing the "toggle" mode of the °ip-°op, so the fact that the J and K
11.3. SYNCHRONOUS COUNTERS 309
inputs must both be (at times) "high" is clear. However, if we simply connect all the J and K inputs
to the positive rail of the power supply as we did in the asynchronous circuit, this would clearly not
work because all the °ip-°ops would toggle at the same time: with each and every clock pulse!
J Q
Q
C
K
Vdd
J Q
Q
C
K
Vdd
J Q
Q
C
K
Vdd
J Q
Q
C
K
Vdd
Q0 Q1 Q2 Q3
This circuit will not function as a counter!
Let's examine the four-bit binary counting sequence again, and see if there are any other patterns
that predict the toggling of a bit. Asynchronous counter circuit design is based on the fact that
each bit toggle happens at the same time that the preceding bit toggles from a "high" to a "low"
(from 1 to 0). Since we cannot clock the toggling of a bit based on the toggling of a previous bit in a
synchronous counter circuit (to do so would create a ripple e®ect) we must ¯nd some other pattern
in the counting sequence that can be used to trigger a bit toggle:
Examining the four-bit binary count sequence, another predictive pattern can be seen. Notice
that just before a bit toggles, all preceding bits are "high:"
0 0 0 0
0 0 0 1
0 0
0 0
1 0
1 1
1
1
1
1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0
0
1 0
1 1
1
1
1
1
0 0
0 1
1 0
1 1
This pattern is also something we can exploit in designing a counter circuit. If we enable each
J-K °ip-°op to toggle based on whether or not all preceding °ip-°op outputs (Q) are "high," we can
obtain the same counting sequence as the asynchronous circuit without the ripple e®ect, since each
310 CHAPTER 11. COUNTERS
°ip-°op in this circuit will be clocked at exactly the same time:
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3
Vdd
This flip-flop This flip-flop This flip-flop This flip-flop
toggles on every
clock pulse
toggles only if
Q0 is "high"
toggles only if toggles only if
Q0 AND Q1
are "high"
Q0 AND Q1 AND Q2
are "high"
A four-bit synchronous "up" counter
The result is a four-bit synchronous "up" counter. Each of the higher-order °ip-°ops are made
ready to toggle (both J and K inputs "high") if the Q outputs of all previous °ip-°ops are "high."
Otherwise, the J and K inputs for that °ip-°op will both be "low," placing it into the "latch" mode
where it will maintain its present output state at the next clock pulse. Since the ¯rst (LSB) °ip-°op
needs to toggle at every clock pulse, its J and K inputs are connected to Vcc or Vdd, where they will
be "high" all the time. The next °ip-°op need only "recognize" that the ¯rst °ip-°op's Q output
is high to be made ready to toggle, so no AND gate is needed. However, the remaining °ip-°ops
should be made ready to toggle only when all lower-order output bits are "high," thus the need for
AND gates.
To make a synchronous "down" counter, we need to build the circuit to recognize the appropriate
bit patterns predicting each toggle state while counting down. Not surprisingly, when we examine the
four-bit binary count sequence, we see that all preceding bits are "low" prior to a toggle (following
the sequence from bottom to top):
11.3. SYNCHRONOUS COUNTERS 311
0 0 0 0
0 0 0 1
0 0
0 0
1 0
1 1
1
1
1
1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
0 0 0
0 0 1
0
0
1 0
1 1
1
1
1
1
0 0
0 1
1 0
1 1
Since each J-K °ip-°op comes equipped with a Q' output as well as a Q output, we can use the
Q' outputs to enable the toggle mode on each succeeding °ip-°op, being that each Q' will be "high"
every time that the respective Q is "low:"
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3
Vdd
This flip-flop This flip-flop This flip-flop This flip-flop
toggles on every
clock pulse
toggles only if
Q0 is "high"
toggles only if toggles only if
Q0 AND Q1
are "high"
Q0 AND Q1 AND Q2
are "high"
A four-bit synchronous "down" counter
Taking this idea one step further, we can build a counter circuit with selectable between "up"
and "down" count modes by having dual lines of AND gates detecting the appropriate bit conditions
for an "up" and a "down" counting sequence, respectively, then use OR gates to combine the AND
gate outputs to the J and K inputs of each succeeding °ip-°op:
312 CHAPTER 11. COUNTERS
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3 Vdd
A four-bit synchronous "up/down" counter
J Q
Q
C
K
J Q
Q
C
K
Up/Down
This circuit isn't as complex as it might ¯rst appear. The Up/Down control input line simply
enables either the upper string or lower string of AND gates to pass the Q/Q' outputs to the
succeeding stages of °ip-°ops. If the Up/Down control line is "high," the top AND gates become
enabled, and the circuit functions exactly the same as the ¯rst ("up") synchronous counter circuit
shown in this section. If the Up/Down control line is made "low," the bottom AND gates become
enabled, and the circuit functions identically to the second ("down" counter) circuit shown in this
section.
To illustrate, here is a diagram showing the circuit in the "up" counting mode (all disabled
circuitry shown in grey rather than black):
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3 Vdd
J Q
Q
C
K
J Q
Q
C
K
Vdd
Up/Down
Counter in "up" counting mode
Here, shown in the "down" counting mode, with the same grey coloring representing disabled
circuitry:
J Q
Q
C
K
J Q
Q
C
K
Q0 Q1 Q2 Q3 Vdd
J Q
Q
C
K
J Q
Q
C
K
Vdd
Up/Down
Counter in "down" counting mode
Up/down counter circuits are very useful devices. A common application is in machine mo-
tion control, where devices called rotary shaft encoders convert mechanical rotation into a series of
electrical pulses, these pulses "clocking" a counter circuit to track total motion:
11.3. SYNCHRONOUS COUNTERS 313
Rotary shaft encoder
LED
Light sensor
(phototransistor)
Counter
Q0 Q1 Q2 Q3
As the machine moves, it turns the encoder shaft, making and breaking the light beam between
LED and phototransistor, thereby generating clock pulses to increment the counter circuit. Thus,
the counter integrates, or accumulates, total motion of the shaft, serving as an electronic indication
of how far the machine has moved. If all we care about is tracking total motion, and do not care
to account for changes in the direction of motion, this arrangement will su±ce. However, if we wish
the counter to increment with one direction of motion and decrement with the reverse direction of
motion, we must use an up/down counter, and an encoder/decoding circuit having the ability to
discriminate between di®erent directions.
If we re-design the encoder to have two sets of LED/phototransistor pairs, those pairs aligned such
that their square-wave output signals are 90o out of phase with each other, we have what is known
as a quadrature output encoder (the word "quadrature" simply refers to a 90o angular separation).
A phase detection circuit may be made from a D-type °ip-°op, to distinguish a clockwise pulse
sequence from a counter-clockwise pulse sequence:
Rotary shaft encoder
LED
Light sensor
(phototransistor)
Counter
Q0 Q1 Q2 Q3
D
C
Q
Q
Up/Down
(quadrature output)
When the encoder rotates clockwise, the "D" input signal square-wave will lead the "C" input
square-wave, meaning that the "D" input will already be "high" when the "C" transitions from "low"
to "high," thus setting the D-type °ip-°op (making the Q output "high") with every clock pulse.
A "high" Q output places the counter into the "Up" count mode, and any clock pulses received
by the clock from the encoder (from either LED) will increment it. Conversely, when the encoder
reverses rotation, the "D" input will lag behind the "C" input waveform, meaning that it will be
"low" when the "C" waveform transitions from "low" to "high," forcing the D-type °ip-°op into the
reset state (making the Q output "low") with every clock pulse. This "low" signal commands the
counter circuit to decrement with every clock pulse from the encoder.
314 CHAPTER 11. COUNTERS
This circuit, or something very much like it, is at the heart of every position-measuring circuit
based on a pulse encoder sensor. Such applications are very common in robotics, CNC machine tool
control, and other applications involving the measurement of reversible, mechanical motion.
11.4 Counter modulus
Chapter 12
SHIFT REGISTERS
Contents
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
12.2 shift register, serial-in/serial-out shift . . . . . . . . . . . . . . . . . . . 318
12.2.1 Serial-in/serial-out devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
12.3 shift register, parallel-in, serial-out . . . . . . . . . . . . . . . . . . . . . 327
12.3.1 Parallel-in/serial-out devices . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.3.2 Practical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
12.4 Serial-in, parallel-out shift register . . . . . . . . . . . . . . . . . . . . . 338
12.4.1 Serial-in/ parallel-out devices . . . . . . . . . . . . . . . . . . . . . . . . . 339
12.4.2 Practical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
12.5 Parallel-in, parallel-out, universal shift register . . . . . . . . . . . . . 347
12.5.1 Parallel-in/ parallel-out and universal devices . . . . . . . . . . . . . . . . 351
12.5.2 Practical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
12.6 Ring counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.6.1 Johnson counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
12.7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Original author: Dennis Crunkilton
12.1 Introduction
Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike combinational
logic is not only a®ected by the present inputs, but also, by the prior history. In other words,
sequential logic remembers past events.
Shift registers produce a discrete delay of a digital signal or waveform. A waveform synchronized
to a clock, a repeating square wave, is delayed by "n" discrete clock times, where "n" is the number
of shift register stages. Thus, a four stage shift register delays "data in" by four clocks to "data
315
316 CHAPTER 12. SHIFT REGISTERS
out". The stages in a shift register are delay stages, typically type "D" Flip-Flops or type "JK"
Flip-°ops.
Formerly, very long (several hundred stages) shift registers served as digital memory. This obso-
lete application is reminiscent of the acoustic mercury delay lines used as early computer memory.
Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert
parallel data to serial form. Serial data communications replaces many slow parallel data wires with
a single serial high speed circuit.
Serial data over shorter distances of tens of centimeters, uses shift registers to get data into
and out of microprocessors. Numerous peripherals, including analog to digital converters, digital to
analog converters, display drivers, and memory, use shift registers to reduce the amount of wiring
in circuit boards.
Some specialized counter circuits actually use shift registers to generate repeating waveforms.
Longer shift registers, with the help of feedback generate patterns so long that they look like random
noise, pseudo-noise.
Basic shift registers are classi¯ed by structure according to the following types:
² Serial-in/serial-out
² Serial-in/parallel-out
² Parallel-in/serial-out
² Universal parallel-in/parallel-out
² Ring counter
clock
data in data out
stage A stage B stage C stage D
Serial-in, serial-out shift register with 4-stages
Above we show a block diagram of a serial-in/serial-out shift register, which is 4-stages long.
Data at the input will be delayed by four clock periods from the input to the output of the shift
register.
Data at "data in", above, will be present at the Stage A output after the ¯rst clock pulse. After
the second pulse stage A data is transfered to stage B output, and "data in" is transfered to stage
A output. After the third clock, stage C is replaced by stage B; stage B is replaced by stage A;
and stage A is replaced by "data in". After the fourth clock, the data originally present at "data
in" is at stage D, "output". The "¯rst in" data is "¯rst out" as it is shifted from "data in" to "data
out".
12.1. INTRODUCTION 317
clock
data out
stage A stage B stage C stage D
Parallel-in, serial-out shift register with 4-stages
DA DB DC DD
data in
Data is loaded into all stages at once of a parallel-in/serial-out shift register. The data is then
shifted out via "data out" by clock pulses. Since a 4- stage shift register is shown above, four clock
pulses are required to shift out all of the data. In the diagram above, stage D data will be present
at the "data out" up until the ¯rst clock pulse; stage C data will be present at "data out" between
the ¯rst clock and the second clock pulse; stage B data will be present between the second clock
and the third clock; and stage A data will be present between the third and the fourth clock. After
the fourth clock pulse and thereafter, successive bits of "data in" should appear at "data out" of
the shift register after a delay of four clock pulses.
If four switches were connected to DA through DD, the status could be read into a microprocessor
using only one data pin and a clock pin. Since adding more switches would require no additional
pins, this approach looks attractive for many inputs.
clock
data out
stage A stage B stage C stage D
Parallel-in, serial-out shift register with 4-stages
QA QB QC QD
data in
Above, four data bits will be shifted in from "data in" by four clock pulses and be available at
QA through QD for driving external circuitry such as LEDs, lamps, relay drivers, and horns.
After the ¯rst clock, the data at "data in" appears at QA. After the second clock, The old QA
data appears at QB; QA receives next data from "data in". After the third clock, QB data is at
QC. After the fourth clock, QC data is at QD. This sat the data ¯rst present at "data in". The
shift register should now contain four data bits.
318 CHAPTER 12. SHIFT REGISTERS
clock
data out
stage A stage B stage C stage D
Parallel-in, parallel-out shift register with 4-stages
QA QB QC QD
data in
DA DB DC DD
mode
A parallel-in/laralel-out shift register combines the function of the parallel-in, serial-out shift
register with the function of the serial-in, parallel-out shift register to yields the universal shift
register. The "do anything" shifter comes at a price{ the increased number of I/O (Input/Output)
pins may reduce the number of stages which can be packaged.
Data presented at DA through DD is parallel loaded into the registers. This data at QA through
QD may be shifted by the number of pulses presented at the clock input. The shifted data is available
at QA through QD. The "mode" input, which may be more than one input, controls parallel loading
of data from DA through DD, shifting of data, and the direction of shifting. There are shift registers
which will shift data either left or right.
clock
data in
data out
stage A stage B stage C stage D
Ring Counter, shift register output fed back to input
QD
If the serial output of a shift register is connected to the serial input, data can be perpetually
shifted around the ring as long as clock pulses are present. If the output is inverted before being fed
back as shown above, we do not have to worry about loading the initial data into the "ring counter".
12.2 shift register, serial-in/serial-out shift
Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a bit
of data for each register. A serial-in, serial-out shift register may be one to 64 bits in length, longer
if registers or packages are cascaded.
Below is a single stage shift register receiving data which is not synchronized to the register clock.
The "data in" at the D pin of the type D FF (Flip-Flop) does not change levels when the clock
12.2. SHIFT REGISTER, SERIAL-IN/SERIAL-OUT SHIFT 319
changes for low to high. We may want to synchronize the data to a system wide clock in a circuit
board to improve the reliability of a digital logic circuit.
D
C
Q
data in Q
clock
Data present at clock time is transfered from D to Q.
QA
data in
clock
t1 t2 t3 t4
The obvious point (as compared to the ¯gure below) illustrated above is that whatever "data
in" is present at the D pin of a type D FF is transfered from D to output Q at clock time. Since
our example shift register uses positive edge sensitive storage elements, the output Q follows the D
input when the clock transitions from low to high as shown by the up arrows on the diagram above.
There is no doubt what logic level is present at clock time because the data is stable well before and
after the clock edge. This is seldom the case in multi-stage shift registers. But, this was an easy
example to start with. We are only concerned with the positive, low to high, clock edge. The falling
edge can be ignored. It is very easy to see Q follow D at clock time above. Compare this to the
diagram below where the "data in" appears to change with the positive clock edge.
D
C
Q
data in Q
clock
Does the clock t1 see a 0 or a 1 at data in at D? Which output is correct,
QC or QW ?
QC
data in
clock
t1 t2 t3
QW
?
?
?
?
Since "data in" appears to changes at clock time t1 above, what does the type D FF see at clock
time? The short over simpli¯ed answer is that it sees the data that was present at D prior to the
clock. That is what is transfered to Q at clock time t1. The correct waveform is QC. At t1 Q goes
to a zero if it is not already zero. The D register does not see a one until time t2, at which time Q
goes high.
320 CHAPTER 12. SHIFT REGISTERS
D
C
Q
data in Q
clock
Data present tH before clock time at D is transfered to Q.
QA
data in
clock
t1 t2 t3 t4
delay of 1 clock
period
Since data, above, present at D is clocked to Q at clock time, and Q cannot change until the next
clock time, the D FF delays data by one clock period, provided that the data is already synchronized
to the clock. The QA waveform is the same as "data in" with a one clock period delay.
A more detailed look at what the input of the type D Flip-Flop sees at clock time follows. Refer
to the ¯gure below. Since "data in" appears to changes at clock time (above), we need further
information to determine what the D FF sees. If the "data in" is from another shift register stage,
another same type D FF, we can draw some conclusions based on data sheet information. Manu-
facturers of digital logic make available information about their parts in data sheets, formerly only
available in a collection called a data book. Data books are still available; though, the manufacturer's
web site is the modern source.
clock
tS tH
Q tP
data in D
Data must be present (tS) before the clock and after(tH) the clock. Data is
delayed from D to Q by propagation delay (tP)
The following data was extracted from the CD4006b data sheet for operation at 5VDC, which
serves as an example to illustrate timing.
(http://focus.ti.com/docs/prod/folders/print/cd4006b.html)
² tS=100ns
² tH=60ns
² tP =200-400ns typ/max
12.2. SHIFT REGISTER, SERIAL-IN/SERIAL-OUT SHIFT 321
tS is the setup time, the time data must be present before clock time. In this case data must be
present at D 100ns prior to the clock. Furthermore, the data must be held for hold time tH=60ns
after clock time. These two conditions must be met to reliably clock data from D to Q of the
Flip-Flop.
There is no problem meeting the setup time of 60ns as the data at D has been there for the
whole previous clock period if it comes from another shift register stage. For example, at a clock
frequency of 1 Mhz, the clock period is 1000 ¹s, plenty of time. Data will actually be present for
1000¹s prior to the clock, which is much greater than the minimum required tS of 60ns.
The hold time tH=60ns is met because D connected to Q of another stage cannot change any
faster than the propagation delay of the previous stage tP =200ns. Hold time is met as long as the
propagation delay of the previous D FF is greater than the hold time. Data at D driven by another
stage Q will not change any faster than 200ns for the CD4006b.
To summarize, output Q follows input D at nearly clock time if Flip-Flops are cascaded into a
multi-stage shift register.
D
C
Q
Q D
C
Q
Q D
C
Q
Q
QA QB QC
data in data out
clock
Serial-in, serial-out shift register using type "D" storage elements
Three type D Flip-Flops are cascaded Q to D and the clocks paralleled to form a three stage
shift register above.
J
C
K Q
Q J
C
K Q
Q J
C
K Q
data in Q
clock
Serial-in, serial-out shift register using type "JK" storage elements
QA QB QC
data out
Type JK FFs cascaded Q to J, Q' to K with clocks in parallel to yield an alternate form of the
shift register above.
A serial-in/serial-out shift register has a clock input, a data input, and a data output from the
last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in,
parallel-out shift register..
322 CHAPTER 12. SHIFT REGISTERS
The waveforms below are applicable to either one of the preceding two versions of the serial-in,
serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily
stores 3-bits of data and delays it by three clock periods from input to output.
QA
QB
QC
data in
clock
t1 t2 t3 t4
At clock time t1 a "data in" of 0 is clocked from D to Q of all three stages. In particular, D of
stage A sees a logic 0, which is clocked to QA where it remains until time t2.
At clock time t2 a "data in" of 1 is clocked from D to QA. At stages B and C, a 0, fed from
preceding stages is clocked to QB and QC.
At clock time t3 a "data in" of 0 is clocked from D to QA. QA goes low and stays low for the
remaining clocks due to "data in" being 0. QB goes high at t3 due to a 1 from the previous stage.
QC is still low after t3 due to a low from the previous stage.
QC ¯nally goes high at clock t4 due to the high fed to D from the previous stage QB. All earlier
stages have 0s shifted into them. And, after the next clock pulse at t5, all logic 1s will have been
shifted out, replaced by 0s
12.2.1 Serial-in/serial-out devices
We will take a closer look at the following parts available as integrated circuits, courtesy of Texas
Instruments. For complete device data sheets follow the links.
² CD4006b 18-bit serial-in/ serial-out shift register
(http://focus.ti.com/docs/prod/folders/print/cd4006b.html)
² CD4031b 64-bit serial-in/ serial-out shift register
(http://focus.ti.com/docs/prod/folders/print/cd4031b.html)
² CD4517b dual 64-bit serial-in/ serial-out shift register
(http://focus.ti.com/docs/prod/folders/print/cd4517b.html)
The following serial-in/ serial-out shift registers are 4000 series CMOS (Complementary Metal
Oxide Semiconductor) family parts. As such, They will accept a VDD, positive power supply of
3-Volts to 15-Volts. The VSS pin is grounded. The maximum frequency of the shift clock, which
varies with VDD, is a few megahertz. See the full data sheet for details.
12.2. SHIFT REGISTER, SERIAL-IN/SERIAL-OUT SHIFT 323
clock
4 12
CL
1 D1 D1+4 13
D2 D2 +5
CL
6 9
5 D3 D3+4 10
D4 D4 +5
3
11
D2 +4 D4 +4
8
2
latch
CL
CL and CL to all 18-stages & latch.
CL
VSS ( pin 7) = Gnd, VDD (pin 14) = +3 to +18 VDC
CD4006b Serial-in/ serial-out shift register
CL
CL
CL
CL
CL
CL
The 18-bit CD4006b consists of two stages of 4-bits and two more stages of 5-bits with a an
output tap at 4-bits. Thus, the 5-bit stages could be used as 4-bit shift registers. To get a full 18-bit
shift register the output of one shift register must be cascaded to the input of another and so on
until all stages create a single shift register as shown below.
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VSS
VDD
D1 D2 D3 D4
Clock
D1+4
D1+4 delayed
D4+4
D4+5
D3+4
D2+4
D2+5
cl
CD4006b 18-bit serial-in/ serial-out shift register
D
Q
+5V
Clock
Data
Out
324 CHAPTER 12. SHIFT REGISTERS
A CD4031 64-bit serial-in/ serial-out shift register is shown below. A number of pins are not
connected (nc). Both Q and Q' are available from the 64th stage, actually Q64 and Q'64. There is
also a Q64 "delayed" from a half stage which is delayed by half a clock cycle. A major feature is a
data selector which is at the data input to the shift register.
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD
Data 2 VSS
clock Q64 Q64
Q64 delayed
Data 1 mode control
D Q
Q
Q D
64-stages
nc nc nc nc
nc nc
CLD
delayed clock out
C
CD4031 64-bit serial-in/ serial-out shift register
The "mode control" selects between two inputs: data 1 and data 2. If "mode control" is high,
data will be selected from "data 2" for input to the shift register. In the case of "mode control"
being logic low, the "data 1" is selected. Examples of this are shown in the two ¯gures below.
12.2. SHIFT REGISTER, SERIAL-IN/SERIAL-OUT SHIFT 325
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Data 2 VSS
clock
Q64 Q64
mode control
Data 1 = logic high
D Q
Q
Q D
64-stages
nc nc nc nc
nc nc
CLD
delayed clock out
C
CD4031 64-bit serial-in/ serial-out shift register recirculating data.
VDD
VDD
mode control
clock
t1 t2 t3 t4
clock
Q64
64 clocks 64 clocks
The "data 2" above is wired to the Q64 output of the shift register. With "mode control" high,
the Q64 output is routed back to the shifter data input D. Data will recirculate from output to input.
The data will repeat every 64 clock pulses as shown above. The question that arises is how did this
data pattern get into the shift register in the ¯rst place?
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VSS
Data
2 clock Q64 Q64
mode control
= logic low
data 1
D Q
Q
Q D
64-stages
nc nc nc nc
nc nc
CLD
delayed clock out
C
CD4031 64-bit serial-in/ serial-out shift register load new data at Data 1.
VDD
VDD
mode control
Q64
data 1
clock
t1 t2 t64 t65
326 CHAPTER 12. SHIFT REGISTERS
With "mode control" low, the CD4031 "data 1" is selected for input to the shifter. The output,
Q64, is not recirculated because the lower data selector gate is disabled. By disabled we mean that
the logic low "mode select" inverted twice to a low at the lower NAND gate prevents it for passing
any signal on the lower pin (data 2) to the gate output. Thus, it is disabled.
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD
Q32A DA VSS
D
DB
C
CD4517b dual 64-bit serial-in/ serial-out shift register
Q48A WEA CLA Q64A
Q16B Q48B WEB CL8 Q64B Q32B
Q16A
D
C
16 32 48 64
16 32 48 64
WE
WE
3 to 18 VDC
GND
A CD4517b dual 64-bit shift register is shown above. Note the taps at the 16th, 32nd, and 48th
stages. That means that shift registers of those lengths can be con¯gured from one of the 64-bit
shifters. Of course, the 64-bit shifters may be cascaded to yield an 80-bit, 96-bit, 112-bit, or 128-bit
shift register. The clock CLA and CLB need to be paralleled when cascading the two shifters. WEB
and WEB are grounded for normal shifting operations. The data inputs to the shift registers A and
B are DA and DB respectively.
Suppose that we require a 16-bit shift register. Can this be con¯gured with the CD4517b? How
about a 64-shift register from the same part?
12.3. SHIFT REGISTER, PARALLEL-IN, SERIAL-OUT 327
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD
Q32A DA VSS
D
DB
C
CD4517b dual 64-bit serial-in/ serial-out shift register, wired for
16-shift register, 64-bit shift register
Q48A WEA CLA
Q16B Q48B
WEB CL8 Q64B Q32B
Q16A
D
C
16 32 48 64
16 32 48 64
WE
WE
5V
Q16B out
Q64A
Q64A out
clock
data in
clock
data in
Above we show A CD4517b wired as a 16-bit shift register for section B. The clock for section
B is CLB. The data is clocked in at CLB. And the data delayed by 16-clocks is picked of o® Q16B.
WEB , the write enable, is grounded.
Above we also show the same CD4517b wired as a 64-bit shift register for the independent section
A. The clock for section A is CLA. The data enters at CLA. The data delayed by 64-clock pulses is
picked up from Q64A. WEA, the write enable for section A, is grounded.
12.3 shift register, parallel-in, serial-out
Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift registers
do plus input data to all stages simultaneously. The parallel-in/ serial-out shift register stores data,
shifts it on a clock by clock basis, and delays it by the number of stages times the clock period. In
addition, parallel-in/ serial-out really means that we can load data in parallel into all stages before
any shifting ever begins. This is a way to convert data from a parallel format to a serial format. By
parallel format we mean that the data bits are present simultaneously on individual wires, one for
each data bit as shown below. By serial format we mean that the data bits are presented sequentially
in time on a single wire or circuit as in the case of the "data out" on the block diagram below.
328 CHAPTER 12. SHIFT REGISTERS
clock
data out
stage A stage B stage C stage D
Parallel-in, serial-out shift register with 4-stages
DA DB DC DD
data in
Below we take a close look at the internal details of a 3-stage parallel-in/ serial-out shift register.
A stage consists of a type D Flip-Flop for storage, and an AND-OR selector to determine whether
data will load in parallel, or shift stored data to the right. In general, these elements will be replicated
for the number of stages required. We show three stages due to space limitations. Four, eight or
sixteen bits is normal for real parts.
D
C
Q
Q D
C
Q
Q D
C
Q
Q
QC
SI
CLK
SHIFT/LD = 0
SO
Parallel-in/ serial-out shift register showing parallel load path
QA QB
DA DB DC
Above we show the parallel load path when SHIFT/LD' is logic low. The upper NAND gates
serving DA DB DC are enabled, passing data to the D inputs of type D Flip-Flops QA QB DC
respectively. At the next positive going clock edge, the data will be clocked from D to Q of the three
FFs. Three bits of data will load into QA QB DC at the same time.
The type of parallel load just described, where the data loads on a clock pulse is known as
synchronous load because the loading of data is synchronized to the clock. This needs to be dif-
ferentiated from asynchronous load where loading is controlled by the preset and clear pins of the
Flip-Flops which does not require the clock. Only one of these load methods is used within an
individual device, the synchronous load being more common in newer devices.
D
C
Q
Q D
C
Q
Q D
C
Q
Q
QA QB QC
DA DB DC
SI
CLK
SHIFT/LD = 1
SO
Parallel-in/ serial-out shift register showing shift path
DAA
DBB DCC
12.3. SHIFT REGISTER, PARALLEL-IN, SERIAL-OUT 329
The shift path is shown above when SHIFT/LD' is logic high. The lower AND gates of the pairs
feeding the OR gate are enabled giving us a shift register connection of SI to DA , QA to DB , QB
to DC , QC to SO. Clock pulses will cause data to be right shifted out to SO on successive pulses.
The waveforms below show both parallel loading of three bits of data and serial shifting of this
data. Parallel data at DA DB DC is converted to serial data at SO.
DA
DB
DC
data in
clock
t1 t2 t3 t4
SHIFT/LD
Parallel-in/ serial-out shift register load/shift waveforms
QA
QB
QC (SO)
1
0
1
1
0
1
What we previously described with words for parallel loading and shifting is now set down as
waveforms above. As an example we present 101 to the parallel inputs DAA DBB DCC. Next, the
SHIFT/LD' goes low enabling loading of data as opposed to shifting of data. It needs to be low a
short time before and after the clock pulse due to setup and hold requirements. It is considerably
wider than it has to be. Though, with synchronous logic it is convenient to make it wide. We could
have made the active low SHIFT/LD' almost two clocks wide, low almost a clock before t1 and back
high just before t3. The important factor is that it needs to be low around clock time t1 to enable
parallel loading of the data by the clock.
Note that at t1 the data 101 at DA DB DC is clocked from D to Q of the Flip-Flops as shown
at QA QB QC at time t1. This is the parallel loading of the data synchronous with the clock.
330 CHAPTER 12. SHIFT REGISTERS
DA
DB
DC
data in
clock
t1 t2 t3 t4
SHIFT/LD
Parallel-in/ serial-out shift register load/shift waveforms
QA
QB
1
0
1
1
0
QC (SO) 1 0 1
Now that the data is loaded, we may shift it provided that SHIFT/LD' is high to enable shifting,
which it is prior to t2. At t2 the data 0 at QC is shifted out of SO which is the same as the QC
waveform. It is either shifted into another integrated circuit, or lost if there is nothing connected to
SO. The data at QB, a 0 is shifted to QC. The 1 at QA is shifted into QB. With "data in" a 0, QA
becomes 0. After t2, QA QB QC = 010.
After t3, QA QB QC = 001. This 1, which was originally present at QA after t1, is now present
at SO and QC. The last data bit is shifted out to an external integrated circuit if it exists. After t4
all data from the parallel load is gone. At clock t5 we show the shifting in of a data 1 present on
the SI, serial input.
Why provide SI and SO pins on a shift register? These connections allow us to cascade shift
register stages to provide large shifters than available in a single IC (Integrated Circuit) package.
They also allow serial connections to and from other ICs like microprocessors.
12.3.1 Parallel-in/serial-out devices
Let's take a closer look at parallel-in/ serial-out shift registers available as integrated circuits, cour-
tesy of Texas Instruments. For complete device data sheets follow these the links.
² SN74ALS166 parallel-in/ serial-out 8-bit shift register, synchronous load
(http://www-s.ti.com/sc/ds/sn74als166.pdf)
² SN74ALS165 parallel-in/ serial-out 8-bit shift register, asynchronous load
(http://www-s.ti.com/sc/ds/sn74als165.pdf)
² CD4014B parallel-in/ serial-out 8-bit shift register, synchronous load
(http://www-s.ti.com/sc/ds/cd4014b.pdf)
12.3. SHIFT REGISTER, PARALLEL-IN, SERIAL-OUT 331
² SN74LS647 parallel-in/ serial-out 16-bit shift register, synchronous load
(http://www-s.ti.com/sc/ds/sn74ls674.pdf)
D
C
Q
Q D
C
Q
Q D
C
Q
Q
QH
SER
CLK
SH/LD
SN74ALS166 Parallel-in/ serial-out 8-bit shift register
QA QB
A B H
CLR
CLKINH
The SN74ALS166 shown above is the closest match of an actual part to the previous parallel-in/
serial out shifter ¯gures. Let us note the minor changes to our ¯gure above. First of all, there are
8-stages. We only show three. All 8-stages are shown on the data sheet available at the link above.
The manufacturer labels the data inputs A, B, C, and so on to H. The SHIFT/LOAD control is
called SH/LD'. It is abbreviated from our previous terminology, but works the same: parallel load if
low, shift if high. The shift input (serial data in) is SER on the ALS166 instead of SI. The clock CLK
is controlled by an inhibit signal, CLKINH. If CLKINH is high, the clock is inhibited, or disabled.
Otherwise, this "real part" is the same as what we have looked at in detail.
R SRG8
M1 [Shift]
M2 [Load]
³1 C3/1
1, 3D
2, 3D
2, 3D
13 QH
9
15
6
7
2
3
4
5
10
11
12
14
SER 1
A
B
C
D
E
F
G
H
CLR
SH/LD
CLKINH
CLK
SN74ALS166 ANSI Symbol
Above is the ANSI (American National Standards Institute) symbol for the SN74ALS166 as
provided on the data sheet. Once we know how the part operates, it is convenient to hide the details
within a symbol. There are many general forms of symbols. The advantage of the ANSI symbol is
that the labels provide hints about how the part operates.
The large notched block at the top of the '74ASL166 is the control section of the ANSI symbol.
There is a reset indicted by R. There are three control signals: M1 (Shift), M2 (Load), and C3/1
332 CHAPTER 12. SHIFT REGISTERS
(arrow) (inhibited clock). The clock has two functions. First, C3 for shifting parallel data wherever
a pre¯x of 3 appears. Second, whenever M1 is asserted, as indicated by the 1 of C3/1 (arrow),
the data is shifted as indicated by the right pointing arrow. The slash (/) is a separator between
these two functions. The 8-shift stages, as indicated by title SRG8, are identi¯ed by the external
inputs A, B, C, to H. The internal 2, 3D indicates that data, D, is controlled by M2 [Load] and
C3 clock. In this case, we can conclude that the parallel data is loaded synchronously with the clock
C3. The upper stage at A is a wider block than the others to accommodate the input SER. The
legend 1, 3D implies that SER is controlled by M1 [Shift] and C3 clock. Thus, we expect to clock
in data at SER when shifting as opposed to parallel loading.
³1 ³1 &
ANSI gate symbols
&
The ANSI/IEEE basic gate rectangular symbols are provided above for comparison to the more
familiar shape symbols so that we may decipher the meaning of the symbology associated with the
CLKINH and CLK pins on the previous ANSI SN74ALS166 symbol. The CLK and CLKINH feed
an OR gate on the SN74ALS166 ANSI symbol. OR is indicated by => on the rectangular inset
symbol. The long triangle at the output indicates a clock. If there was a bubble with the arrow this
would have indicated shift on negative clock edge (high to low). Since there is no bubble with the
clock arrow, the register shifts on the positive (low to high transition) clock edge. The long arrow,
after the legend C3/1 pointing right indicates shift right, which is down the symbol.
D
C
Q
Q D
C
Q
SER Q
CLK
SH/LD
SN74ALS165 Parallel-in/ serial-out 8-bit shift register,
asynchronous load
QA QB
CLKINH
R
S
R
S D
C
Q
Q
QH
R
S
A B H
12.3. SHIFT REGISTER, PARALLEL-IN, SERIAL-OUT 333
Part of the internal logic of the SN74ALS165 parallel-in/ serial-out, asynchronous load shift
register is reproduced from the data sheet above. See the link at the beginning of this section the
for the full diagram. We have not looked at asynchronous loading of data up to this point. First of
all, the loading is accomplished by application of appropriate signals to the Set (preset) and Reset
(clear) inputs of the Flip-Flops. The upper NAND gates feed the Set pins of the FFs and also
cascades into the lower NAND gate feeding the Reset pins of the FFs. The lower NAND gate
inverts the signal in going from the Set pin to the Reset pin.
First, SH/LD' must be pulled Low to enable the upper and lower NAND gates. If SH/LD'
were at a logic high instead, the inverter feeding a logic low to all NAND gates would force a
High out, releasing the "active low" Set and Reset pins of all FFs. There would be no possibility
of loading the FFs.
With SH/LD' held Low, we can feed, for example, a data 1 to parallel input A, which inverts
to a zero at the upper NAND gate output, setting FF QA to a 1. The 0 at the Set pin is fed to
the lower NAND gate where it is inverted to a 1 , releasing the Reset pin of QA. Thus, a data
A=1 sets QA=1. Since none of this required the clock, the loading is asynchronous with respect
to the clock. We use an asynchronous loading shift register if we cannot wait for a clock to parallel
load data, or if it is inconvenient to generate a single clock pulse.
The only di®erence in feeding a data 0 to parallel input A is that it inverts to a 1 out of the
upper gate releasing Set. This 1 at Set is inverted to a 0 at the lower gate, pulling Reset to a
Low, which resets QA=0.
SRG8
C1 [LOAD]
³1 C2/
2D
1D
1D
6 QH
1
15
2
11
12
13
14
3
4
5
6
SER 10
A
B
C
D
E
F
G
H
SH/LD
CLKINH
CLK
SN74ALS165 ANSI Symbol
1D
7 QH
The ANSI symbol for the SN74ALS166 above has two internal controls C1 [LOAD] and C2
clock from the OR function of (CLKINH, CLK). SRG8 says 8-stage shifter. The arrow after C2
indicates shifting right or down. SER input is a function of the clock as indicated by internal label
2D. The parallel data inputs A, B, C to H are a function of C1 [LOAD], indicated by internal label
1D. C1 is asserted when sh/LD' =0 due to the half-arrow inverter at the input. Compare this to
the control of the parallel data inputs by the clock of the previous synchronous ANSI SN75ALS166.
Note the di®erences in the ANSI Data labels.
334 CHAPTER 12. SHIFT REGISTERS
SRG8
M1 [Shift]
M2 [Load]
C3/1
1, 3D
2, 3D
2, 3D
3 Q8
9
10
7
6
5
4
13
14
15
1
SER 11
P1
P2
P3
P4
P5
P6
P7
P8
CLK
12
2
Q7
Q6
LD/SH
SRG8
C1 [Load]
³1 C2/
2D
1D
3 Q8
9
10
7
6
5
4
13
14
15
1
SER 11
P1
P2
P3
P4
P5
P6
P7
P8
CLK
12
2
Q7
Q6
LD/SH
CD4021B, asynchronous load
CMOS Parallel-in/ serial-out shift registers, 8-bit ANSI symbols
1D
2, 3D 1D
CD4014B, synchronous load
On the CD4014B above, M1 is asserted when LD/SH'=0. M2 is asserted when LD/SH'=1.
Clock C3/1 is used for parallel loading data at 2, 3D when M2 is active as indicated by the 2,3
pre¯x labels. Pins P3 to P7 are understood to have the smae internal 2,3 pre¯x labels as P2 and
P8. At SER, the 1,3D pre¯x implies that M1 and clock C3 are necessary to input serial data.
Right shifting takes place when M1 active is as indicated by the 1 in C3/1 arrow.
The CD4021B is a similar part except for asynchronous parallel loading of data as implied by
the lack of any 2 pre¯x in the data label 1D for pins P1, P2, to P8. Of course, pre¯x 2 in label 2D
at input SER says that data is clocked into this pin. The OR gate inset shows that the clock is
controlled by LD/SH'.
12.3. SHIFT REGISTER, PARALLEL-IN, SERIAL-OUT 335
SRG 16
G1/2 EN
& C4/3
3,4D
6 SER/Q15
1
8
9
14
15
P1
P2
P3
P4
P5
P6
P7
P8
CLK
CS
SN74LS674, parallel-in/serial-out, synchronous load
MODE
R/W
74LS674
3
5
2
1,2 M3
G2
3,4D
3,4D
7
13
11
10
16
3,4D
P9
P10 18
20
22
17
19
21
23
P11
P12
P13
P14
P15
P0
The above SN74LS674 internal label SRG 16 indicates 16-bit shift register. The MODE input
to the control section at the top of the symbol is labeled 1,2 M3. Internal M3 is a function of
input MODE and G1 and G2 as indicated by the 1,2 preceding M3. The base label G indicates
an AND function of any such G inputs. Input R/W' is internally labeled G1/2 EN. This is an
enable EN (controlled by G1 AND G2) for tristate devices used elsewhere in the symbol. We
note that CS' on (pin 1) is internal G2. Chip select CS' also is ANDed with the input CLK to
give internal clock C4. The bubble within the clock arrow indicates that activity is on the negative
(high to low transition) clock edge. The slash (/) is a separator implying two functions for the clock.
Before the slash, C4 indicates control of anything with a pre¯x of 4. After the slash, the 3' (arrow)
indicates shifting. The 3' of C4/3' implies shifting when M3 is de-asserted (MODE=0). The long
arrow indicates shift right (down).
Moving down below the control section to the data section, we have external inputs P0-P15,
pins (7-11, 13-23). The pre¯x 3,4 of internal label 3,4D indicates that M3 and the clock C4 control
loading of parallel data. The D stands for Data. This label is assumed to apply to all the parallel
inputs, though not explicitly written out. Locate the label 3',4D on the right of the P0 (pin7)
stage. The complemented-3 indicates that M3=MODE=0 inputs (shifts) SER/Q15 (pin5) at
clock time, (4 of 3',4D) corresponding to clock C4. In other words, with MODE=0, we shift data
into Q0 from the serial input (pin 6). All other stages shift right (down) at clock time.
336 CHAPTER 12. SHIFT REGISTERS
Moving to the bottom of the symbol, the triangle pointing right indicates a bu®er between Q and
the output pin. The Triangle pointing down indicates a tri-state device. We previously stated that
the tristate is controlled by enable EN, which is actually G1 AND G2 from the control section.
If R/W=0, the tri-state is disabled, and we can shift data into Q0 via SER (pin 6), a detail we
omitted above. We actually need MODE=0, R/W'=0, CS'=0
The internal logic of the SN74LS674 and a table summarizing the operation of the control signals
is available in the link in the bullet list, top of section.
If R/W'=1, the tristate is enabled, Q15 shifts out SER/Q15 (pin 6) and recirculates to the Q0
stage via the right hand wire to 3',4D. We have assumed that CS' was low giving us clock C4/3'
and G2 to ENable the tri-state.
12.3.2 Practical applications
An application of a parallel-in/ serial-out shift register is to read data into a microprocessor.
1 2 3
4 5 6
7 8 9
Keypad Alarm
Gnd
Clock
Serial data
+5V
Alarm with remote keypad
The Alarm above is controlled by a remote keypad. The alarm box supplies +5V and ground to
the remote keypad to power it. The alarm reads the remote keypad every few tens of milliseconds
by sending shift clocks to the keypad which returns serial data showing the status of the keys via
a parallel-in/ serial-out shift register. Thus, we read nine key switches with four wires. How many
wires would be required if we had to run a circuit for each of the nine keys?
12.3. SHIFT REGISTER, PARALLEL-IN, SERIAL-OUT 337
SRG8
C1 [Load]
³1 C2/
2D
1D
3 Q8
9
10
7
6
5
4
13
14
15
1
11
SER
P1
P2
P3
P4
P5
P6
P7
P8
CLK
12
2
Q7
Q6
LD/SH
CD4021B
1D
1D
+5V
+5V
microprocessor
+5V
Shift clock
Load/shift
Serial data in
Reading switches into microprocessor
Other serial or gnd
Serial data in
Load/shift
Shift clock
P8
P7P6
P4
P3
P2
P1
P5
A practical application of a parallel-in/ serial-out shift register is to read many switch closures into
a microprocessor on just a few pins. Some low end microprocessors only have 6-I/O (Input/Output)
pins available on an 8-pin package. Or, we may have used most of the pins on an 84-pin package.
We may want to reduce the number of wires running around a circuit board, machine, vehicle, or
building. This will increase the reliability of our system. It has been reported that manufacturers
who have reduced the number of wires in an automobile produce a more reliable product. In any
event, only three microprocessor pins are required to read in 8-bits of data from the switches in the
¯gure above.
We have chosen an asynchronous loading device, the CD4021B because it is easier to control the
loading of data without having to generate a single parallel load clock. The parallel data inputs of
the shift register are pulled up to +5V with a resistor on each input. If all switches are open, all
1s will be loaded into the shift register when the microprocessor moves the LD/SH' line from low
to high, then back low in anticipation of shifting. Any switch closures will apply logic 0s to the
corresponding parallel inputs. The data pattern at P1-P7 will be parallel loaded by the LD/SH'=1
generated by the microprocessor software.
The microprocessor generates shift pulses and reads a data bit for each of the 8-bits. This
process may be performed totally with software, or larger microprocessors may have one or more
serial interfaces to do the task more quickly with hardware. With LD/SH'=0, the microprocessor
generates a 0 to 1 transition on the Shift clock line, then reads a data bit on the Serial data in
line. This is repeated for all 8-bits.
The SER line of the shift register may be driven by another identical CD4021B circuit if more
switch contacts need to be read. In which case, the microprocessor generates 16-shift pulses. More
likely, it will be driven by something else compatible with this serial data format, for example, an
analog to digital converter, a temperature sensor, a keyboard scanner, a serial read-only memory. As
for the switch closures, they may be limit switches on the carriage of a machine, an over-temperature
sensor, a magnetic reed switch, a door or window switch, an air or water pressure switch, or a solid
338 CHAPTER 12. SHIFT REGISTERS
state optical interrupter.
12.4 Serial-in, parallel-out shift register
A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts
data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is di®erent
in that it makes all the internal stages available as outputs. Therefore, a serial-in/parallel-out shift
register converts data from serial format to parallel format. If four data bits are shifted in by four
clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the
four Outputs QA to QD after the fourth clock pulse.
clock
data out
stage A stage B stage C stage D
Parallel-in, serial-out shift register with 4-stages
QA QB QC QD
data in
The practical application of the serial-in/parallel-out shift register is to convert data from serial
format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate four LEDs
(Light Emitting Diodes) with the four outputs (QA QB QC QD ).
R
1D
R
QA
R
QB QD
SI
CLK
CLR
R
QC
SO
Serial-in/ Parallel out shift register details
1D 1D 1D
The above details of the serial-in/parallel-out shift register are fairly simple. It looks like a
serial-in/ serial-out shift register with taps added to each stage output. Serial data shifts in at SI
(Serial Input). After a number of clocks equal to the number of stages, the ¯rst data bit in appears
12.4. SERIAL-IN, PARALLEL-OUT SHIFT REGISTER 339
at SO (QD) in the above ¯gure. In general, there is no SO pin. The last stage (QD above) serves as
SO and is cascaded to the next package if it exists.
If a serial-in/parallel-out shift register is so similar to a serial-in/ serial-out shift register, why do
manufacturers bother to o®er both types? Why not just o®er the serial-in/parallel-out shift register?
They actually only o®er the serial-in/parallel-out shift register, as long as it has no more than 8-bits.
Note that serial-in/ serial-out shift registers come in gigger than 8-bit lengths of 18 to to 64-bits. It
is not practical to o®er a 64-bit serial-in/parallel-out shift register requiring that many output pins.
See waveforms below for above shift register.
SI
CLK
t1 t2 t3 t4
Serial-in/ parallel-out shift register waveforms
QA
QB
QC
1 0 1
1 0 1
1 0
1
CLR
1
QD
1
0
1
1
t5 t6 t7 t8
The shift register has been cleared prior to any data by CLR', an active low signal, which clears
all type D Flip-Flops within the shift register. Note the serial data 1011 pattern presented at the SI
input. This data is synchronized with the clock CLK. This would be the case if it is being shifted
in from something like another shift register, for example, a parallel-in/ serial-out shift register (not
shown here). On the ¯rst clock at t1, the data 1 at SI is shifted from D to Q of the ¯rst shift
register stage. After t2 this ¯rst data bit is at QB. After t3 it is at QC. After t4 it is at QD. Four
clock pulses have shifted the ¯rst data bit all the way to the last stage QD. The second data bit a
0 is at QC after the 4th clock. The third data bit a 1 is at QB. The fourth data bit another 1 is at
QA. Thus, the serial data input pattern 1011 is contained in (QD QC QB QA). It is now available
on the four outputs.
It will available on the four outputs from just after clock t4 to just before t5. This parallel data
must be used or stored between these two times, or it will be lost due to shifting out the QD stage
on following clocks t5 to t8 as shown above.
12.4.1 Serial-in/ parallel-out devices
Let's take a closer look at Serial-in/ parallel-out shift registers available as integrated circuits, cour-
tesy of Texas Instruments. For complete device data sheets follow the links.
340 CHAPTER 12. SHIFT REGISTERS
² SN74ALS164A serial-in/ parallel-out 8-bit shift register
(http://www-s.ti.com/sc/ds/sn74als164a.pdf)
² SN74AHC594 serial-in/ parallel-out 8-bit shift register with output register
(http://www-s.ti.com/sc/ds/sn74ahct594.pdf)
² SN74AHC595 serial-in/ parallel-out 8-bit shift register with output register
(http://www-s.ti.com/sc/ds/sn74ahct595.pdf)
² CD4094 serial-in/ parallel-out 8-bit shift register with output register
(http://www-s.ti.com/sc/ds/cd4094b.pdf)
(http://www.st.com/stonline/books/pdf/docs/2069.pdf)
R
1R
1S
R
1R
1S
QA
R
1R
1S
QB QH
A
B
CLK
CLR
Serial-in/ Parallel out shift register details
The 74ALS164A is almost identical to our prior diagram with the exception of the two serial
inputs A and B. The unused input should be pulled high to enable the other input. We do not show
all the stages above. However, all the outputs are shown on the ANSI symbol below, along with the
pin numbers.
12.4. SERIAL-IN, PARALLEL-OUT SHIFT REGISTER 341
SRG8
R
C1/
9
8
11
12
13
3
4
5
6
10
A
QA
QB
QC
QD
QE
QF
QG
QH
CLR
CLK
SN74ALS164A ANSI Symbol
2
1
B & 1D
The CLK input to the control section of the above ANSI symbol has two internal functions C1,
control of anything with a pre¯x of 1. This would be clocking in of data at 1D. The second function,
the arrow after after the slash (/) is right (down) shifting of data within the shift register. The eight
outputs are available to the right of the eight registers below the control section. The ¯rst stage is
wider than the others to accommodate the A&B input.
R
QA QB
SER
SRCLK
SRCLR
R
74AHC594 Serial-in/ Parallel out 8-bit shift register with output registers
1D 1D
R
1D
R
1D
R
1D
R
1D
QH’
RCLR
RCLK
QH
14
11
10
13
12
15 1 7
QC QD QE QF QG
2 3 4 5 6
9
QA’ QB’
342 CHAPTER 12. SHIFT REGISTERS
The above internal logic diagram is adapted from the TI (Texas Instruments) data sheet for the
74AHC594. The type "D" FFs in the top row comprise a serial-in/ parallel-out shift register. This
section works like the previously described devices. The outputs (QA' QB' to QH' ) of the shift
register half of the device feed the type "D" FFs in the lower half in parallel. QH' (pin 9) is shifted
out to any optional cascaded device package.
A single positive clock edge at RCLK will transfer the data from D to Q of the lower FFs. All
8-bits transfer in parallel to the output register (a collection of storage elements). The purpose of
the output register is to maintain a constant data output while new data is being shifted into the
upper shift register section. This is necessary if the outputs drive relays, valves, motors, solenoids,
horns, or buzzers. This feature may not be necessary when driving LEDs as long as °icker during
shifting is not a problem.
Note that the 74AHC594 has separate clocks for the shift register (SRCLK) and the output
register ( RCLK). Also, the shifter may be cleared by SRCLR and, the output register by RCLR.
It desirable to put the outputs in a known state at power-on, in particular, if driving relays, motors,
etc. The waveforms below illustrate shifting and latching of data.
SI
SRCLK
t1 t2 t3 t4
Waveforms for 74AHC594 serial-in/ parallel-out shift registe rwith latch
QA’
QB’
QC’
1 0 1
1 0 1
1 0
1
RCLR
1
QD’ 1
0
1
1
t5 t6 t7 t8
QA
QB
QC
QD
RCLK
1
0
1
1
CLR
12.4. SERIAL-IN, PARALLEL-OUT SHIFT REGISTER 343
The above waveforms show shifting of 4-bits of data into the ¯rst four stages of 74AHC594, then
the parallel transfer to the output register. In actual fact, the 74AHC594 is an 8-bit shift register,
and it would take 8-clocks to shift in 8-bits of data, which would be the normal mode of operation.
However, the 4-bits we show saves space and adequately illustrates the operation.
We clear the shift register half a clock prior to t0 with SRCLR'=0. SRCLR' must be released
back high prior to shifting. Just prior to t0 the output register is cleared by RCLR'=0. It, too,
is released ( RCLR'=1).
Serial data 1011 is presented at the SI pin between clocks t0 and t4. It is shifted in by clocks t1
t2 t3 t4 appearing at internal shift stages QA' QB' QC' QD' . This data is present at these stages
between t4 and t5. After t5 the desired data (1011) will be unavailable on these internal shifter
stages.
Between t4 and t5 we apply a positive going RCLK transferring data 1011 to register outputs
QA QB QC QD . This data will be frozen here as more data (0s) shifts in during the succeeding
SRCLKs (t5 to t8). There will not be a change in data here until another RCLK is applied.
R
QA QB
SER
SRCLK
SRCLR
R
74AHC595 Serial-in/ Parallel out 8-bit shift register with output registers
1D 1D 1D
1D 1D 1D
QH’
RCLK
QH
14
11
10
12
15 1 7
QC QD QE QF QG
2 3 4 5 6
9
OE
13
Q Q Q
Q Q Q
The 74AHC595 is identical to the '594 except that the RCLR' is replaced by an OE' enabling
a tri-state bu®er at the output of each of the eight output register bits. Though the output register
cannot be cleared, the outputs may be disconnected by OE'=1. This would allow external pull-up
or pull-down resistors to force any relay, solenoid, or valve drivers to a known state during a system
power-up. Once the system is powered-up and, say, a microprocessor has shifted and latched data
into the '595, the output enable could be asserted (OE'=0) to drive the relays, solenoids, and valves
with valid data, but, not before that time.
344 CHAPTER 12. SHIFT REGISTERS
SRG8
C3/
13
11
5
6
7
15
1
2
3
4
SER QA
QB
QC
QD
QE
QF
QG
QH
SRCLK
SN74AHC594 ANSI Symbol
14 2,3D
QH’ 9
RCLK 12 C4
1,4D
2D
2D
RCLR R1
SRCLR 10 R2
1,4D
SRG8
C3/
13
11
5
6
7
15
1
2
3
4
QA
QB
QC
QD
QE
QF
QG
QH
SN74AHC595 ANSI Symbol
14 2,3D
QH’ 9
12 C4
4D
2D
2D
EN
10 R2
4D
SER
SRCLK
RCLK
OE
SRCLR
Above are the proposed ANSI symbols for these devices. C3 clocks data into the serial input
(external SER) as indicate by the 3 pre¯x of 2,3D. The arrow after C3/ indicates shifting right
(down) of the shift register, the 8-stages to the left of the '595symbol below the control section. The
2 pre¯x of 2,3D and 2D indicates that these stages can be reset by R2 (external SRCLR').
The 1 pre¯x of 1,4D on the '594 indicates that R1 (external RCLR') may reset the output
register, which is to the right of the shift register section. The '595, which has an EN at external
OE' cannot reset the output register. But, the EN enables tristate (inverted triangle) output
bu®ers. The right pointing triangle of both the '594 and'595 indicates internal bu®ering. Both the
'594 and'595 output registers are clocked by C4 as indicated by 4 of 1,4D and 4D respectively.
SRG8
C1/
13
11
5
6
7
15
2
3
4
SERIAL OUT
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CLOCK
CD4094B/ 74HCT4094 ANSI Symbol
14
1D
QS’
9
STROBE
12
C2
2D
OUTPUT
10
3
1
ENABLE EN3
QS
SERIAL OUT
SERIAL
IN
The CD4094B is a 3 to 15VDC capable latching shift register alternative to the previous 74AHC594
devices. CLOCK, C1, shifts data in at SERIAL IN as implied by the 1 pre¯x of 1D. It is also
12.4. SERIAL-IN, PARALLEL-OUT SHIFT REGISTER 345
the clock of the right shifting shift register (left half of the symbol body) as indicated by the /(right-
arrow) of C1/(arrow) at the CLOCK input.
STROBE, C2 is the clock for the 8-bit output register to the right of the symbol body. The
2 of 2D indicates that C2 is the clock for the output register. The inverted triangle in the output
latch indicates that the output is tristated, being enabled by EN3. The 3 preceding the inverted
triangle and the 3 of EN3 are often omitted, as any enable (EN) is understood to control the
tristate outputs.
QS and QS' are non-latched outputs of the shift register stage. QS could be cascaded to
SERIAL IN of a succeeding device.
12.4.2 Practical applications
A real-world application of the serial-in/ parallel-out shift register is to output data from a micro-
processor to a remote panel indicator. Or, another remote output device which accepts serial format
data.
1 2 3
4 5 6
7 8 9
Keypad Alarm
Gnd
Clock
Serial data
+5V
Alarm with remote keypad and display
Remote display
The ¯gure "Alarm with remote key pad" is repeated here from the parallel-in/ serial-out section
with the addition of the remote display. Thus, we can display, for example, the status of the alarm
loops connected to the main alarm box. If the Alarm detects an open window, it can send serial data
to the remote display to let us know. Both the keypad and the display would likely be contained
within the same remote enclosure, separate from the main alarm box. However, we will only look
at the display panel in this section.
If the display were on the same board as the Alarm, we could just run eight wires to the eight
LEDs along with two wires for power and ground. These eight wires are much less desirable on
a long run to a remote panel. Using shift registers, we only need to run ¯ve wires- clock, serial
data, a strobe, power, and ground. If the panel were just a few inches away from the main board,
it might still be desirable to cut down on the number of wires in a connecting cable to improve
reliability. Also, we sometimes use up most of the available pins on a microprocessor and need to
use serial techniques to expand the number of outputs. Some integrated circuit output devices, such
as Digital to Analog converters contain serial-in/ parallel-out shift registers to receive data from
microprocessors. The techniques illustrated here are applicable to those parts.
346 CHAPTER 12. SHIFT REGISTERS
microprocessor
+5V
Shift clock
Output to LEDs from microprocessor
SRG8
C3/
13
11
5
6
7
15
1
2
3
4
SER QA
QB
QC
QD
QE
QF
QG
QH
SRCLK
14 2,3D
9 QH’
RCLK 12 C4
1,4D
2D
2D
RCLR R1
SRCLR 10 R2
1,4D
74AHC594
Serial data out
+5V
LatchLEDdata
+5V 470W x8
We have chosen the 74AHC594 serial-in/ parallel-out shift register with output register; though,
it requires an extra pin, RCLK, to parallel load the shifted-in data to the output pins. This extra
pin prevents the outputs from changing while data is shifting in. This is not much of a problem for
LEDs. But, it would be a problem if driving relays, valves, motors, etc.
Code executed within the microprocessor would start with 8-bits of data to be output. One bit
would be output on the "Serial data out" pin, driving SER of the remote 74AHC594. Next, the
microprocessor generates a low to high transition on "Shift clock", driving SRCLK of the '595 shift
register. This positive clock shifts the data bit at SER from "D" to "Q" of the ¯rst shift register
stage. This has no e®ect on the QA LED at this time because of the internal 8-bit output register
between the shift register and the output pins (QA to QH). Finally, "Shift clock" is pulled back low
by the microprocessor. This completes the shifting of one bit into the '595.
The above procedure is repeated seven more times to complete the shifting of 8-bits of data from
the microprocessor into the 74AHC594 serial-in/ parallel-out shift register. To transfer the 8-bits of
data within the internal '595 shift register to the output requires that the microprocessor generate
a low to high transition on RCLK, the output register clock. This applies new data to the LEDs.
The RCLK needs to be pulled back low in anticipation of the next 8-bit transfer of data.
The data present at the output of the '595 will remain until the process in the above two
paragraphs is repeated for a new 8-bits of data. In particular, new data can be shifted into the '595
internal shift register without a®ecting the LEDs. The LEDs will only be updated with new data
with the application of the RCLK rising edge.
What if we need to drive more than eight LEDs? Simply cascade another 74AHC594 SER pin to
the QH' of the existing shifter. Parallel the SRCLK and RCLK pins. The microprocessor would
need to transfer 16-bits of data with 16-clocks before generating an RCLK feeding both devices.
The discrete LED indicators, which we show, could be 7-segment LEDs. Though, there are LSI
(Large Scale Integration) devices capable of driving several 7-segment digits. This device accepts
data from a microprocessor in a serial format, driving more LED segments than it has pins by by
multiplexing the LEDs. For example, see link below for MAX6955
(http://www.maxim-ic.com/appnotes.cfm/appnote number/3211)
12.5. PARALLEL-IN, PARALLEL-OUT, UNIVERSAL SHIFT REGISTER 347
12.5 Parallel-in, parallel-out, universal shift register
The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then
output it as shown below. A universal shift register is a do-everything device in addition to the
parallel-in/ parallel-out function.
clock
data out
stage A stage B stage C stage D
Parallel-in, parallel-out shift register with 4-stages
QA QB QC QD
data in
DA DB DC DD
mode
Above we apply four bit of data to a parallel-in/ parallel-out shift register at DA DB DC DD.
The mode control, which may be multiple inputs, controls parallel loading vs shifting. The mode
control may also control the direction of shifting in some real devices. The data will be shifted one
bit position for each clock pulse. The shifted data is available at the outputs QA QB QC QD .
The "data in" and "data out" are provided for cascading of multiple stages. Though, above, we can
only cascade data for right shifting. We could accommodate cascading of left-shift data by adding
a pair of left pointing signals, "data in" and "data out", above.
The internal details of a right shifting parallel-in/ parallel-out shift register are shown below.
The tri-state bu®ers are not strictly necessary to the parallel-in/ parallel-out shift register, but are
part of the real-world device shown below.
QA QB
DA DB
SER
CLK
LD/SH
DC
QD
CLR
OC
QD’
Cascade
74LS395 parallel-in/ parallel-out shift register with tri-state output
QC
DD
348 CHAPTER 12. SHIFT REGISTERS
The 74LS395 so closely matches our concept of a hypothetical right shifting parallel-in/ parallel-
out shift register that we use an overly simpli¯ed version of the data sheet details above. See the
link to the full data sheet more more details, later in this chapter.
LD/SH' controls the AND-OR multiplexer at the data input to the FF's. If LD/SH'=1, the
upper four AND gates are enabled allowing application of parallel inputs DA DB DC DD to the
four FF data inputs. Note the inverter bubble at the clock input of the four FFs. This indicates
that the 74LS395 clocks data on the negative going clock, which is the high to low transition. The
four bits of data will be clocked in parallel from DA DB DC DD to QA QB QC QD at the next
negative going clock. In this "real part", OC' must be low if the data needs to be available at the
actual output pins as opposed to only on the internal FFs.
The previously loaded data may be shifted right by one bit position if LD/SH'=0 for the
succeeding negative going clock edges. Four clocks would shift the data entirely out of our 4-bit
shift register. The data would be lost unless our device was cascaded from QD' to SER of another
device.
QA QB QC QD
1 1 0 1
X 1 1 0
X X 1 1
load
shift
shift
Load and shift Load and 2-shifts
load
shift
Parallel-in/ parallel-out shift register
QA QB QC QD
1 1 0 1
X 1 1 0
DA DB DC DD
data 1 1 0 1
DA DB DC DD
data 1 1 0 1
Above, a data pattern is presented to inputs DA DB DC DD. The pattern is loaded to QA QB
QC QD . Then it is shifted one bit to the right. The incoming data is indicated by X, meaning the
we do no know what it is. If the input (SER) were grounded, for example, we would know what
data (0) was shifted in. Also shown, is right shifting by two positions, requiring two clocks.
D
C
Q
Q D
C
Q
Q D
C
Q
Q
QA QB QC
SI
SO
Shift right
CLK
The above ¯gure serves as a reference for the hardware involved in right shifting of data. It is
too simple to even bother with this ¯gure, except for comparison to more complex ¯gures to follow.
12.5. PARALLEL-IN, PARALLEL-OUT, UNIVERSAL SHIFT REGISTER 349
Load and right shift
load
shift
QA QB QC
1 1 0
X 1 1
Right shifting of data is provided above for reference to the previous right shifter.
D
C
Q
Q D
C
Q
Q D
C
Q
Q
QA QB QC
SI
SO
Shift left
CLK
If we need to shift left, the FFs need to be rewired. Compare to the previous right shifter.
Also, SI and SO have been reversed. SI shifts to QC. QC shifts to QB. QB shifts to QA. QA
leaves on the SO connection, where it could cascade to another shifter SI. This left shift sequence
is backwards from the right shift sequence.
Load and left shift
load
shift
QA QB QC
1 1 0
1 0 X
Above we shift the same data pattern left by one bit.
There is one problem with the "shift left" ¯gure above. There is no market for it. Nobody
manufactures a shift-left part. A "real device" which shifts one direction can be wired externally to
shift the other direction. Or, should we say there is no left or right in the context of a device which
shifts in only one direction. However, there is a market for a device which will shift left or right on
command by a control line. Of course, left and right are valid in that context.
350 CHAPTER 12. SHIFT REGISTERS
QB
CLK
L/R
Shift left/ right, right action
SR
D Q
Ck
D Q
Ck
R L
QC’
SR
cascade
D Q
Ck
R L R L
SL
cascade
SL
QA
QC
(L/R=1)
What we have above is a hypothetical shift register capable of shifting either direction under the
control of L'/R. It is setup with L'/R=1 to shift the normal direction, right. L'/R=1 enables
the multiplexer AND gates labeled R. This allows data to follow the path illustrated by the arrows,
when a clock is applied. The connection path is the same as the"too simple" "shift right" ¯gure
above.
Data shifts in at SR, to QA, to QB, to QC, where it leaves at SR cascade. This pin could
drive SR of another device to the right.
What if we change L'/R to L'/R=0?
QB
CLK
L/R
Shift left/ right register, left action
SR
D Q
Ck
D Q
Ck
R L
QC’
SR
cascade
D Q
Ck
R L R L
SL
cascade
SL
QA
QC
(L/R=0)
With L'/R=0, the multiplexer AND gates labeled L are enabled, yielding a path, shown by the
arrows, the same as the above "shift left" ¯gure. Data shifts in at SL, to QC, to QB, to QA, where
it leaves at SL cascade. This pin could drive SL of another device to the left.
12.5. PARALLEL-IN, PARALLEL-OUT, UNIVERSAL SHIFT REGISTER 351
The prime virtue of the above two ¯gures illustrating the "shift left/ right register" is simplicity.
The operation of the left right control L'/R=0 is easy to follow. A commercial part needs the
parallel data loading implied by the section title. This appears in the ¯gure below.
DA
CLK
L/R
Shift left/ right/ load
SH/LD
SR
D Q
Ck
D Q
Ck
R L load
DB
R L load
SL
D Q
Ck
DC
R L load
SR
cascade
SL
cascade
QA QB QC
Now that we can shift both left and right via L'/R, let us add SH/LD', shift/ load, and the
AND gates labeled "load" to provide for parallel loading of data from inputs DA DB DC. When
SH/LD'=0, AND gates R and L are disabled, AND gates "load" are enabled to pass data DA DB
DC to the FF data inputs. the next clock CLK will clock the data to QA QB QC. As long as the
same data is present it will be re-loaded on succeeding clocks. However, data present for only one
clock will be lost from the outputs when it is no longer present on the data inputs. One solution
is to load the data on one clock, then proceed to shift on the next four clocks. This problem is
remedied in the 74ALS299 by the addition of another AND gate to the multiplexer.
If SH/LD' is changed to SH/LD'=1, the AND gates labeled "load" are disabled, allowing the
left/ right control L'/R to set the direction of shift on the L or R AND gates. Shifting is as in the
previous ¯gures.
The only thing needed to produce a viable integrated device is to add the fourth AND gate to
the multiplexer as alluded for the 74ALS299. This is shown in the next section for that part.
12.5.1 Parallel-in/ parallel-out and universal devices
Let's take a closer look at Serial-in/ parallel-out shift registers available as integrated circuits, cour-
tesy of Texas Instruments. For complete device data sheets, follow the links.
² SN74LS395A parallel-in/ parallel-out 4-bit shift register
(http://www-s.ti.com/sc/ds/sn74ls395a.pdf)
352 CHAPTER 12. SHIFT REGISTERS
² SN74ALS299 parallel-in/ parallel-out 8-bit universal shift register
(http://www-s.ti.com/sc/ds/sn74als299.pdf)
R SRG4
C3/2
1
7
15
14
13
12
SER
QA
QB
QC
QD
CLR
CLK
SN74LS395A ANSI Symbol
3
2
A
OC EN4
LD/SH
10
9
B
C
D
4
5
6
11 QD’
M2 (SHIFT)
M1 (LOAD)
2,3D
4
1,3D
4
1,3D
We have already looked at the internal details of the SN74LS395A, see above previous ¯gure,
74LS395 parallel-in/ parallel-out shift register with tri-state output. Directly above is the ANSI
symbol for the 74LS395.
Why only 4-bits, as indicated by SRG4 above? Having both parallel inputs, and parallel outputs,
in addition to control and power pins, does not allow for any more I/O (Input/Output) bits in a
16-pin DIP (Dual Inline Package).
R indicates that the shift register stages are reset by input CLR' (active low- inverting half arrow
at input) of the control section at the top of the symbol. OC', when low, (invert arrow again) will
enable (EN4) the four tristate output bu®ers (QA QB QC QD ) in the data section. Load/shift'
(LD/SH') at pin (7) corresponds to internals M1 (load) and M2 (shift). Look for pre¯xes of 1
and 2 in the rest of the symbol to ascertain what is controlled by these.
The negative edge sensitive clock (indicated by the invert arrow at pin-10) C3/2has two func-
tions. First, the 3 of C3/2 a®ects any input having a pre¯x of 3, say 2,3D or 1,3D in the data
section. This would be parallel load at A, B, C, D attributed to M1 and C3 for 1,3D. Second, 2
of C3/2-right-arrow indicates data clocking wherever 2 appears in a pre¯x (2,3D at pin-2). Thus
we have clocking of data at SER into QA with mode 2 . The right arrow after C3/2 accounts for
shifting at internal shift register stages QA QB QC QD.
The right pointing triangles indicate bu®ering; the inverted triangle indicates tri-state, controlled
by the EN4. Note, all the 4s in the symbol associated with the EN are frequently omitted. Stages
QB QC are understood to have the same attributes as QD. QD' cascades to the next package's
SER to the right.
mode mux
activity S1 S0 clock gate
hold 0 0 ­ hold
shift left 0 1 ­ L
shift right 1 0 ­ R
load 1 1 ­ load
S1 S0 OE2 OE1 tristate
X X X 1 disable
X X 1 X disable
0 0 0 0 enable
0 1 0 0 enable
1 0 0 0 enable
1 1 X X disable
12.5. PARALLEL-IN, PARALLEL-OUT, UNIVERSAL SHIFT REGISTER 353
The table above, condensed from the data '299 data sheet, summarizes the operation of the
74ALS299 universal shift/ storage register. Follow the '299 link above for full details. The Multi-
plexer gates R, L, load operate as in the previous "shift left/ right register" ¯gures. The di®erence
is that the mode inputs S1 and S0 select shift left, shift right, and load with mode set to S1 S0
= to 01, 10, and 11respectively as shown in the table, enabling multiplexer gates L, R, and load
respectively. See table. A minor di®erence is the parallel load path from the tri-state outputs.
Actually the tri-state bu®ers are (must be) disabled by S1 S0 = 11 to °oat the I/O bus for use as
inputs. A bus is a collection of similar signals. The inputs are applied to A, B through H (same
pins as QA, QB, through QH) and routed to the load gate in the multiplexers, and on the the D
inputs of the FFs. Data is parallel load on a clock pulse.
The one new multiplexer gate is the AND gate labeled hold, enabled by S1 S0 = 00. The hold
gate enables a path from the Q output of the FF back to the hold gate, to the D input of the same
FF. The result is that with mode S1 S0 = 00, the output is continuously re-loaded with each new
clock pulse. Thus, data is held. This is summarized in the table.
To read data from outputs QA, QB, through QH, the tri-state bu®ers must be enabled by OE2',
OE1' =00 and mode =S1 S0 = 00, 01, or 10. That is, mode is anything except load. See second
table.
QH’
DA
OE1
CLK
S0
74ALS299 universal shift/ storage register with tri-state outputs
H/QH
QA’
OE2
S1
SR
SL
CLR
A/QA
D Q
R
Ck
D Q
R
Ck
R L load R L load
6-stages
omitted
hold hold
Right shift data from a package to the left, shifts in on the SR input. Any data shifted out to
the right from stage QH cascades to the right via QH'. This output is una®ected by the tri-state
bu®ers. The shift right sequence for S1 S0 = 10 is:
SR > QA > QB > QC > QD > QE > QF > QG > QH (QH')
354 CHAPTER 12. SHIFT REGISTERS
Left shift data from a package to the right shifts in on the SL input. Any data shifted out to the
left from stage QA cascades to the left via QA', also una®ected by the tri-state bu®ers. The shift
left sequence for S1 S0 = 01 is:
(QA') QA < QB < QC < QD < QE < QF < QG < QH (QSL')
Shifting may take place with the tri-state bu®ers disabled by one of OE2' or OE1' = 1. Though,
the register contents outputs will not be accessible. See table.
C4/1
SN74ALS299 ANSI Symbol
3,4D 1,4D
6,13
17 QH’
SRG8
& 3EN13
0 0
1 3
M
R
3,4D
1,4D
3,4D
12,13
2,4D
8 QA’
Z5
Z6
Z12
CLR
9
OE1
2
OE2
3
SO
1
S1
19
CLK
12
SR
11
A/QA
7
6
14
5
13
4
16
15
SL
18
5,13
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
/2
The "clean" ANSI symbol for the SN74ALS299 parallel-in/ parallel-out 8-bit universal shift
register with tri-state output is shown for reference above.
12.5. PARALLEL-IN, PARALLEL-OUT, UNIVERSAL SHIFT REGISTER 355
C4/1
SN74ALS299 ANSI Symbol, annotated
3,4D 1,4D
6,13
17 QH’
SRG8
& 3EN13
0 0
1 3
M
R
3,4D
1,4D
3,4D
12,13
2,4D
8 QA’
Z5
Z6
Z12
CLR
9
OE1
2
OE2
3
SO
1
S1
19
CLK
12
SR
11
A/QA
7
6
14
5
13
4
16
15
SL
18
5,13
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
/2
mode3 SO S1 M
O O O
O 1 1
1 O 2
1 1 3
function
hold
shift right
load
shift left
EN13=mode3 & OE1 & OE2
enable tri-state buffers
prefix 1 implies right shift
prefix 2 implies left shift
prefix 3,4D implies mode-3 parallel
load by C4
Z5, Z6 to Z12 are tri-state outputs of the
shift register stages associated with the
I/O pins A/QA, B/QB, to Q/QH as implied
by prefixes 5,13; 6,13; to 12,13 respectively.
4 as a prefix (4D) implies clocking of
data by C4, as opposed to shifting
A double arrow implies bidirectional
data, equivalent to the input (no arrow)
and output (single arrow).
is buffer
is tri-state
The annotated version of the ANSI symbol is shown to clarify the terminology contained therein.
Note that the ANSI mode (S0 S1) is reversed from the order (S1 S0) used in the previous table.
That reverses the decimal mode numbers (1 & 2). In any event, we are in complete agreement with
the o±cial data sheet, copying this inconsistency.
12.5.2 Practical applications
The Alarm with remote keypad block diagram is repeated below. Previously, we built the keypad
reader and the remote display as separate units. Now we will combine both the keypad and display
into a single unit using a universal shift register. Though separate in the diagram, the Keypad and
Display are both contained within the same remote enclosure.
1 2 3
4 5 6
7 8 9
Keypad Alarm
Gnd
Clock
Serial data
+5V
Alarm with remote keypad and display
Remote display
356 CHAPTER 12. SHIFT REGISTERS
We will parallel load the keyboard data into the shift register on a single clock pulse, then shift
it out to the main alarm box. At the same time , we will shift LED data from the main alarm to
the remote shift register to illuminate the LEDs. We will be simultaneously shifting keyboard data
out and LED data into the shift register.
C4/1
74ALS299 universal shift register reads switches, drives LEDs
3,4D 1,4D
6,13
QH’
17
SRG8
& 3EN13
0 0
1 3
M
R
3,4D
1,4D
3,4D
12,13
2,4D
8 QA’
Z5
Z6
Z12
CLR 9
OE1 2
OE2
3
SO 1
S1 19
CLK 12
SR 11
A/QA 7
6
14
5
13
4
16
15
SL
18
5,13
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
/2
470 W x8
+5V
S1
CLK
SO
SR
2.2K W
+5V
S1 S0 mode
0 0 hold
0 1 L
1 0 R
1 1 load
1
19
2
18 17 16 15 14 13 12 11
3 4 5 6 7 8 9
74ALS541
74ALS299
Eight LEDs and current limiting resistors are connected to the eight I/O pins of the 74ALS299
universal shift register. The LEDS can only be driven during Mode 3 with S1=0 S0=0. The OE1'
and OE2' tristate enables are grounded to permenantly enable the tristate outputs during modes
0, 1, 2. That will cause the LEDS to light (°icker) during shifting. If this were a problem the
EN1' and EN2' could be ungrounded and paralleled with S1 and S0 respectively to only enable
the tristate bu®ers and light the LEDS during hold, mode 3. Let's keep it simple for this example.
During parallel loading, S0=1 inverted to a 0, enables the octal tristate bu®ers to ground the
switch wipers. The upper, open, switch contacts are pulled up to logic high by the resister-LED
combination at the eight inputs. Any switch closure will short the input low. We parallel load the
switch data into the '299 at clock t0 when both S0 and S1 are high. See waveforms below.
12.6. RING COUNTERS 357
t0
S1
S0
shift right
load
hold hold
S1 S0 mode
0 0 hold
0 1 L
1 0 R
1 1 load
Load (t0) & shift (t1-t8) switches out of QH’, shift LED data into SR
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11
Once S0 goes low, eight clocks (t0 tot8) shift switch closure data out of the '299 via the Qh'
pin. At the same time, new LED data is shifted in at SR of the 299 by the same eight clocks. The
LED data replaces the switch closure data as shifting proceeds.
After the 8th shift clock, t8, S1 goes low to yield hold mode (S1 S0 = 00). The data in the
shift register remains the same even if there are more clocks, for example, T9, t10, etc. Where
do the waveforms come from? They could be generated by a microprocessor if the clock rate were
not over 100 kHz, in which case, it would be inconvenient to generate any clocks after t8. If the
clock was in the megahertz range, the clock would run continuously. The clock, S1 and S0 would
be generated by digital logic, not shown here.
12.6 Ring counters
If the output of a shift register is fed back to the input. a ring counter results. The data pattern
contained within the shift register will recirculate as long as clock pulses are applied. For example,
the data pattern will repeat every four clock pulses in the ¯gure below. However, we must load
a data pattern. All 0's or all 1's doesn't count. Is a continuous logic level from such a condition
useful?
clock
data in
data out
stage A stage B stage C stage D
Ring Counter, shift register output fed back to input
QD
We make provisions for loading data into the parallel-in/ serial-out shift register con¯gured as
a ring counter below. Any random pattern may be loaded. The most generally useful pattern is a
single 1.
358 CHAPTER 12. SHIFT REGISTERS
clock
data out
stage A stage B stage C stage D
Parallel-in, serial-out shift register configured as
a ring counter
DA DB DC DD
data in
1 0 0 0
Loading binary 1000 into the ring counter, above, prior to shifting yields a viewable pattern.
The data pattern for a single stage repeats every four clock pulses in our 4-stage example. The
waveforms for all four stages look the same, except for the one clock time delay from one stage to
the next. See ¯gure below.
clock
t1 t2 t3 t4
SHIFT/LD
Load 1000 into 4-stage ring counter and shift
QA
QB
QC
QD
t8 t12
1
0
0
0
The circuit above is a divide by 4 counter. Comparing the clock input to any one of the outputs,
shows a frequency ratio of 4:1. How may stages would we need for a divide by 10 ring counter? Ten
stages would recirculate the 1 every 10 clock pulses.
12.6. RING COUNTERS 359
D
C
Q
Q D
C
Q
Q D
C
Q
Q D
C
Q
Q
CLOCK
SET
Set one stage, clear three stages
An alternate method of initializing the ring counter to 1000 is shown above. The shift waveforms
are identical to those above, repeating every fourth clock pulse. The requirement for initialization is
a disadvantage of the ring counter over a conventional counter. At a minimum, it must be initialized
at power-up since there is no way to predict what state °ip-°ops will power up in. In theory,
initialization should never be required again. In actual practice, the °ip-°ops could eventually be
corrupted by noise, destroying the data pattern. A "self correcting" counter, like a conventional
synchronous binary counter would be more reliable.
J Q
Q
C
K
J Q
Q
C
K
5V
CLK
QB QA
GA GB GC GD
Compare to binary synchronous counter with decoder
J K Q
0 0 hold
0 1 0
1 0 1
1 1 toggle
The above binary synchronous counter needs only two stages, but requires decoder gates. The
ring counter had more stages, but was self decoding, saving the decode gates above. Another
disadvantage of the ring counter is that it is not "self starting". If we need the decoded outputs, the
ring counter looks attractive, in particular, if most of the logic is in a single shift register package.
If not, the conventional binary counter is less complex without the decoder.
360 CHAPTER 12. SHIFT REGISTERS
clock
t1 t2 t3 t4
Compare to binary synchronous counter with decode, waveforms
GA
GB
GC
GD
t8 t12
1
0
0
0
QA
QB 1
0
The waveforms decoded from the synchronous binary counter are identical to the previous ring
counter waveforms. The counter sequence is (QA QB) = (00 01 10 11).
12.6.1 Johnson counters
The switch-tail ring counter, also know as the Johnson counter, overcomes some of the limitations
of the ring counter. Like a ring counter a Johnson counter is a shift register fed back on its' self. It
requires half the stages of a comparable ring counter for a given division ratio. If the complement
output of a ring counter is fed back to the input instead of the true output, a Johnson counter
results. The di®erence between a ring counter and a Johnson counter is which output of the last
stage is fed back (Q or Q'). Carefully compare the feedback connection below to the previous ring
counter.
D
C
Q
Q D
C
Q
Q D
C
Q
Q D
C
Q
Q
CLOCK
RESET
Johnson counter (note the QD to DA feedback connection)
QAQBQCQD QA QB QC QD
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
repeat
This "reversed" feedback connection has a profound e®ect upon the behavior of the otherwise
similar circuits. Recirculating a single 1 around a ring counter divides the input clock by a factor
equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice the
number of stages. For example, a 4-stage ring counter divides by 4. A 4-stage Johnson counter
divides by 8.
12.6. RING COUNTERS 361
Start a Johnson counter by clearing all stages to 0s before the ¯rst clock. This is often done at
power-up time. Referring to the ¯gure below, the ¯rst clock shifts three 0s from ( QA QB QC) to
the right into ( QB QC QD). The 1 at QD' (the complement of Q) is shifted back into QA. Thus,
we start shifting 1s to the right, replacing the 0s. Where a ring counter recirculated a single 1, the
4-stage Johnson counter recirculates four 0s then four 1s for an 8-bit pattern, then repeats.
clock
t1 t2 t3 t4
Four stage Johnson counter waveforms
QA
QB
QC
QD
t8 t12 t16
RESET
t5 t6 t7 t0
The above waveforms illustrates that multi-phase square waves are generated by a Johnson
counter. The 4-stage unit above generates four overlapping phases of 50% duty cycle. How many
stages would be required to generate a set of three phase waveforms? For example, a three stage
Johnson counter, driven by a 360 Hertz clock would generate three 120o phased square waves at 60
Hertz.
The outputs of the °op-°ops in a Johnson counter are easy to decode to a single state. Below
for example, the eight states of a 4-stage Johnson counter are decoded by no more than a two input
gate for each of the states. In our example, eight of the two input gates decode the states for our
example Johnson counter.
362 CHAPTER 12. SHIFT REGISTERS
D
C
Q
Q D
C
Q
Q D
C
Q
Q D
C
Q
Q
CLOCK
CLR
Johnson counter with decoder (CD4022B)
QA QB QC QD
QA QBQCQD G
0 0 0 0 G0
1 0 0 0 G1
1 1 0 0 G2
1 1 1 0 G3
1 1 1 1 G4
0 1 1 1 G5
0 0 1 1 G6
0 0 0 1 G7
G0 G5 G2 G7
G4 G1 G6 G3
No matter how long the Johnson counter, only 2-input decoder gates are needed. Note, we could
have used uninverted inputs to the AND gates by changing the gate inputs from true to inverted
at the FFs, Q to Q', (and vice versa). However, we are trying to make the diagram above match
the data sheet for the CD4022B, as closely as practical.
clock
t1 t2 t3 t4
Four stage (8-state) Johnson counter decoder waveforms
QA
QB
QC
QD
t8 t12 t16
G1=QAQB
G2=QBQC
G3=QCQD
G4=QAQD
G5=QAQB
G6=QBQC
G7=QCQD
G0=QAQD
t0 t5 t6 t7
Above, our four phased square waves QA to QD are decoded to eight signals (G0 to G7) active
12.6. RING COUNTERS 363
during one clock period out of a complete 8-clock cycle. For example, G0 is active high when both
QA and QD are low. Thus, pairs of the various register outputs de¯ne each of the eight states of
our Johnson counter example.
D
C
Q
Q D
C
Q
Q D
C
Q
Q D
C
Q
Q
CLOCK
RESET
CD4022B modulo-8 Johnson counter with unused state detector
QA QB QC QD
QA QBQCQD G
0 0 0 0 G0
1 0 0 0 G1
1 1 0 0 G2
1 1 1 0 G3
1 1 1 1 G4
0 1 1 1 G5
0 0 1 1 G6
0 0 0 1 G7
G0 G5 G2 G7
G4 G1 G6 G3
Cout
11 1 5 7 12
2 4 3 10
14
13
10
CLOCK
ENABLE
NOR gate unused state detector: QA QB QC = 010 forces the 1 to a 0
Above is the more complete internal diagram of the CD4022B Johnson counter. See the manu-
facturers' data sheet for minor details omitted. The major new addition to the diagram as compared
to previous ¯gures is the disallowed state detector composed of the two NOR gates. Take a look at
the inset state table. There are 8-permissible states as listed in the table. Since our shifter has four
°ip-°ops, there are a total of 16-states, of which there are 8-disallowed states. That would be the
ones not listed in the table.
In theory, we will not get into any of the disallowed states as long as the shift register is RESET
before ¯rst use. However, in the "real world" after many days of continuous operation due to
unforeseen noise, power line disturbances, near lightning strikes, etc, the Johnson counter could get
into one of the disallowed states. For high reliability applications, we need to plan for this slim
possibility. More serious is the case where the circuit is not cleared at power-up. In this case there
is no way to know which of the 16-states the circuit will power up in. Once in a disallowed state,
the Johnson counter will not return to any of the permissible states without intervention. That is
the purpose of the NOR gates.
364 CHAPTER 12. SHIFT REGISTERS
Examine the table for the sequence (QA QB QC) = (010). Nowhere does this sequence appear
in the table of allowed states. Therefore (010) is disallowed. It should never occur. If it does, the
Johnson counter is in a disallowed state, which it needs to exit to any allowed state. Suppose that
(QA QB QC) = (010). The second NOR gate will replace QB = 1 with a 0 at the D input to
FF QC. In other words, the o®ending 010 is replaced by 000. And 000, which does appear in the
table, will be shifted right. There are may triple-0 sequences in the table. This is how the NOR
gates get the Johnson counter out of a disallowed state to an allowed state.
Not all disallowed states contain a 010 sequence. However, after a few clocks, this sequence will
appear so that any disallowed states will eventually be escaped. If the circuit is powered-up without
a RESET, the outputs will be unpredictable for a few clocks until an allowed state is reached. If
this is a problem for a particular application, be sure to RESET on power-up.
Johnson counter devices
A pair of integrated circuit Johnson counter devices with the output states decoded is available.
We have already looked at the CD4017 internal logic in the discussion of Johnson counters. The
4000 series devices can operate from 3V to 15V power supplies. The the 74HC' part, designed for a
TTL compatiblity, can operate from a 2V to 6V supply, count faster, and has greater output drive
capability. For complete device data sheets, follow the links.
² CD4017 Johnson counter with 10 decoded outputs
CD4022 Johnson counter with 8 decoded outputs
(http://www-s.ti.com/sc/ds/cd4017b.pdf)
² 74HC4017 Johnson counter, 10 decoded outputs
(http://www-s.ti.com/sc/ds/cd74hc4017.pdf)
&
CTR DIV 10/
DEC 0
1
2
3
4
5
6
7
8
9
CD<5
CT=0
CKEN
CK
CLR
13
14
15
3
4
7
2
10
5
6
1
9
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
CD4017B, 74HC4017
&
CTR DIV 8/
OCTAL 0
1
2
3
4
5
6
7
CD<4
CT=0
CKEN
CK
CLR
13
14
15
3
4
7
2
10
5
1
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CO
CD4022B
The ANSI symbols for the modulo-10 (divide by 10) and modulo-8 Johnson counters are shown
above. The symbol takes on the characteristics of a counter rather than a shift register deriva-
tive, which it is. Waveforms for the CD4022 modulo-8 and operation were shown previously. The
CD4017B/ 74HC4017 decade counter is a 5-stage Johnson counter with ten decoded outputs. The
12.6. RING COUNTERS 365
operation and waveforms are similar to the CD4017. In fact, the CD4017 and CD4022 are both
detailed on the same data sheet. See above links. The 74HC4017 is a more modern version of the
decade counter.
These devices are used where decoded outputs are needed instead of the binary or BCD (Binary
Coded Decimal) outputs found on normal counters. By decoded, we mean one line out of the ten
lines is active at a time for the '4017 in place of the four bit BCD code out of conventional counters.
See previous waveforms for 1-of-8 decoding for the '4022 Octal Johnson counter.
Practical applications
&
CTR DIV 10/
DEC 0
1
2
3
4
5
6
7
8
9
CD<5
CT=0
CKEN
CK
CLR
13
14
15
3
4
7
2
10
5
6
1
9
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
74HC4017
555
10K
100K
1mF
1 0.1mF
2
6
7
8 4
3
5
R1
5V
R2
C1
C2
f = 1.46
(R1 +2R2)C
U1
U2
5V
16
8
R=820 W x10
Decoded ring counter drives walking LED
The above Johnson counter shifts a lighted LED each ¯fth of a second around the ring of ten.
Note that the 74HC4017 is used instead of the '40017 because the former part has more current
drive capability. From the data sheet, (at the link above) operating at VCC= 5V, the VOH= 4.6V
at 4ma. In other words, the outputs can supply 4 ma at 4.6 V to drive the LEDs. Keep in mind
that LEDs are normally driven with 10 to 20 ma of current. Though, they are visible down to 1 ma.
This simple circuit illustrates an application of the 'HC4017. Need a bright display for an exhibit?
Then, use inverting bu®ers to drive the cathodes of the LEDs pulled up to the power supply by
lower value anode resistors.
The 555 timer, serving as an astable multivibrator, generates a clock frequency determined by
R1 R2 C1. This drives the 74HC4017 a step per clock as indicated by a single LED illuminated on
the ring. Note, if the 555 does not reliably drive the clock pin of the '4015, run it through a single
bu®er stage between the 555 and the '4017. A variable R2 could change the step rate. The value of
decoupling capacitor C2 is not critical. A similar capacitor should be applied across the power and
ground pins of the '4017.
366 CHAPTER 12. SHIFT REGISTERS
D
C
Q
Q D
C
Q
Q D
C
Q
Q
CLOCK
QA QB QC
Three phase square/ sine wave generator.
low pass filter
low pass filter
low pass filter
f2
f3
f1 P1
CLOCK
P2
P3
P1
P2
P3
QA
QC Disallowed state
The Johnson counter above generates 3-phase square waves, phased 60o apart with respect to
(QA QB QC). However, we need 120o phased waveforms of power applications (see Volume II, AC).
Choosing P1=QA P2=QC P3=QB' yields the 120o phasing desired. See ¯gure below. If these (P1
P2 P3) are low-pass ¯ltered to sine waves and ampli¯ed, this could be the beginnings of a 3-phase
power supply. For example, do you need to drive a small 3-phase 400 Hz aircraft motor? Then, feed
6x 400Hz to the above circuit CLOCK. Note that all these waveforms are 50% duty cycle.
clock
t1 t2 t3 t4
3-stage Johnson counter generates 3-Ø waveform.
QA
QC
t8 t0 t5 t6 t7
P1=QA
QB
P3=QB’
P2=QC
The circuit below produces 3-phase nonoverlapping, less than 50% duty cycle, waveforms for
driving 3-phase stepper motors.
12.6. RING COUNTERS 367
D
C
Q
Q D
C
Q
Q D
C
Q
Q
CLOCK
QA QB QC
P0
P1
P2
P1=QBQC
P2=QAQB
P0=QAQC
3-stage (6-state) Johnson counter decoded for 3-f stepper
motor.
9
1
2
3 14
16
15
VMOTOR
8
U3A
U3B
U3C
part of
ULN2003
QA
QC
Disallowed state
Above we decode the overlapping outputs QA QB QC to non-overlapping outputs P0 P1 P2 as
shown below. These waveforms drive a 3-phase stepper motor after suitable ampli¯cation from the
milliamp level to the fractional amp level using the ULN2003 drivers shown above, or the discrete
component Darlington pair driver shown in the circuit which follow. Not counting the motor driver,
this circuit requires three IC (Integrated Circuit) packages: two dual type "D" FF packages and a
quad NAND gate.
clock
t1 t2 t3 t4
3-stage Johnson counter generates 3-Ø stepper
waveform.
QA
QC
t8 t0 t5 t6 t7
QB
P1=QBQC
P2=QAQB
P0=QAQC
368 CHAPTER 12. SHIFT REGISTERS
&
CTR DIV 10/
DEC 0
1
2
3
4
5
6
7
8
9
CD<5
CT=0
CKEN
CK
CLR
13
14
15
3
4
7
2
10
5
6
1
9
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
CD4017B, 74HC4017
G0
G1
G2
VCC
8
16
VM
Johnson sequence terminated early by reset at Q3, which is high.
for nano seconds
A single CD4017, above, generates the required 3-phase stepper waveforms in the circuit above
by clearing the Johnson counter at count 3. Count 3 persists for less than a microsecond before it
clears its' self. The other counts (Q0=G0 Q1=G1 Q2=G2) remain for a full clock period each.
The Darlington bipolar transistor drivers shown above are a substitute for the internal circuitry
of the ULN2003. The design of drivers is beyond the scope of this digital electronics chapter. Either
driver may be used with either waveform generator circuit.
clock
t1 t2 t3 t4
CD4017B 5-stage (10-state) Johnson counter resetting
at QCQBQA=100 generates 3-f stepper waveform.
QA
QB
QC
t8
Q1=G1=QAQB
Q1=G2=QBQC
Q0=G0=QAQD
t0 t5 t6 t7
G3=QCQD
The above waceforms make the most sense in the context of the internal logic of the CD4017
shown earlier in this section. Though, the AND gating equations for the internal decoder are shown.
The signals QA QB QC are Johnson counter direct shift register outputs not available on pin-outs.
The QD waveform shows resetting of the '4017 every three clocks. Q0 Q1 Q2, etc. are decoded
12.7. REFERENCES 369
outputs which actually are available at output pins.
&
CTR DIV 10/
DEC 0
1
2
3
4
5
6
7
8
9
CD<5
CT=0
CKEN
CK
CLR
13
14
15
3
4
7
2
10
5
6
1
9
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
CD4017B, 74HC4017
VCC
8
16
VM
Johnson counter drives unipolar stepper motor.
9
1
2
3 14
16
15
8 part of
ULN2003
4 13
VM
Above we generate waveforms for driving a unipolar stepper motor, which only requires one
polarity of driving signal. That is, we do not have to reverse the polarity of the drive to the
windings. This simpli¯es the power driver between the '4017 and the motor. Darlington pairs from
a prior diagram may be substituted for the ULN3003.
clock
t1 t2 t3 t4 t8
Q1
Q2
Q0
t0 t5 t6 t7
Q4
Q3
Johnson counter unipolar stepper motor waveforms.
Once again, the CD4017B generates the required waveforms with a reset after the teminal count.
The decoded outputs Q0 Q1 Q2 Q3 sucessively drive the stepper motor windings, with Q4 reseting
the counter at the end of each group of four pulses.
12.7 references
DataSheetCatalog.com http://www.datasheetcatalog.com/
370 CHAPTER 12. SHIFT REGISTERS
http://www.st.com/stonline/psearch/index.htm select standard logics
http://www.st.com/stonline/books/pdf/docs/2069.pdf
http://www.ti.com/ (Products, Logic, Product Tree)
Chapter 13
DIGITAL-ANALOG
CONVERSION
Contents
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
13.2 The R/2nR DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
13.3 The R/2R DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
13.4 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
13.5 Digital ramp ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
13.6 Successive approximation ADC . . . . . . . . . . . . . . . . . . . . . . . 383
13.7 Tracking ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
13.8 Slope (integrating) ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
13.9 Delta-Sigma (¢§) ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
13.10Practical considerations of ADC circuits . . . . . . . . . . . . . . . . . 391
13.1 Introduction
Connecting digital circuitry to sensor devices is simple if the sensor devices are inherently digital
themselves. Switches, relays, and encoders are easily interfaced with gate circuits due to the on/o®
nature of their signals. However, when analog devices are involved, interfacing becomes much more
complex. What is needed is a way to electronically translate analog signals into digital (binary)
quantities, and vice versa. An analog-to-digital converter, or ADC, performs the former task while
a digital-to-analog converter, or DAC, performs the latter.
An ADC inputs an analog electrical signal such as voltage or current and outputs a binary
number. In block diagram form, it can be represented as such:
371
372 CHAPTER 13. DIGITAL-ANALOG CONVERSION
ADC
Vdd
input
Binary
signal output
Analog
A DAC, on the other hand, inputs a binary number and outputs an analog voltage or current
signal. In block diagram form, it looks like this:
Vdd
input
Binary
output
DAC signal
Analog
Together, they are often used in digital systems to provide complete interface with analog sensors
and output devices for control systems such as those used in automotive engine controls:
ADC
Vdd
input
signal
Analog
Vdd Vdd
Control
computer DAC Analog
signal
output
Digital control system with
analog I/O
It is much easier to convert a digital signal into an analog signal than it is to do the reverse.
Therefore, we will begin with DAC circuitry and then move to ADC circuitry.
13.2. THE R/2NR DAC 373
13.2 The R/2nR DAC
This DAC circuit, otherwise known as the binary-weighted-input DAC, is a variation on the inverting
summer op-amp circuit. If you recall, the classic inverting summer circuit is an operational ampli¯er
using negative feedback for controlled gain, with several voltage inputs and one voltage output. The
output voltage is the inverted (opposite polarity) sum of all input voltages:
-
+
R
R
R
V1
V2
V3
Vout
R
I1
I3
I2
0 V I1 + I2 + I3
0 V
Inverting summer circuit
Vout = - (V1 + V2 + V3)
For a simple inverting summer circuit, all resistors must be of equal value. If any of the input
resistors were di®erent, the input voltages would have di®erent degrees of e®ect on the output, and
the output voltage would not be a true sum. Let's consider, however, intentionally setting the input
resistors at di®erent values. Suppose we were to set the input resistor values at multiple powers of
two: R, 2R, and 4R, instead of all the same value R:
-
+
V1
V2
V3
Vout
R
I1
I3
I2
0 V I1 + I2 + I3
0 V
R
2R
4R
Vout = - (V1 +
V2
2
+ V3
4
)
Starting from V1 and going through V3, this would give each input voltage exactly half the e®ect
on the output as the voltage before it. In other words, input voltage V1 has a 1:1 e®ect on the
output voltage (gain of 1), while input voltage V2 has half that much e®ect on the output (a gain of
374 CHAPTER 13. DIGITAL-ANALOG CONVERSION
1/2), and V3 half of that (a gain of 1/4). These ratios are were not arbitrarily chosen: they are the
same ratios corresponding to place weights in the binary numeration system. If we drive the inputs
of this circuit with digital gates so that each input is either 0 volts or full supply voltage, the output
voltage will be an analog representation of the binary value of these three bits.
-
+
V1
V2
V3
Vout
R
I1
I3
I2
0 V I1 + I2 + I3
0 V
R
2R
4R
Binary
input
MSB
LSB
If we chart the output voltages for all eight combinations of binary bits (000 through 111) input
to this circuit, we will get the following progression of voltages:
---------------------------------
j Binary j Output voltage j
---------------------------------
j 000 j 0.00 V j
---------------------------------
j 001 j -1.25 V j
---------------------------------
j 010 j -2.50 V j
---------------------------------
j 011 j -3.75 V j
---------------------------------
j 100 j -5.00 V j
---------------------------------
j 101 j -6.25 V j
---------------------------------
j 110 j -7.50 V j
---------------------------------
j 111 j -8.75 V j
---------------------------------
Note that with each step in the binary count sequence, there results a 1.25 volt change in the
output. This circuit is very easy to simulate using SPICE. In the following simulation, I set up the
DAC circuit with a binary input of 110 (note the ¯rst node numbers for resistors R1, R2, and R3:
a node number of "1" connects it to the positive side of a 5 volt battery, and a node number of "0"
connects it to ground). The output voltage appears on node 6 in the simulation:
13.2. THE R/2NR DAC 375
-
+
6
0
5
0
1
5 V
R1
R2
R3
Rfeedbk
1 kW
2 kW
4 kW
Rbogus 5 6
99 kW
binary-weighted dac
v1 1 0 dc 5
rbogus 1 0 99k
r1 1 5 1k
r2 1 5 2k
r3 0 5 4k
rfeedbk 5 6 1k
e1 6 0 5 0 999k
.end
node voltage node voltage node voltage
(1) 5.0000 (5) 0.0000 (6) -7.5000
We can adjust resistors values in this circuit to obtain output voltages directly corresponding to
the binary input. For example, by making the feedback resistor 800 ­ instead of 1 k­, the DAC
will output -1 volt for the binary input 001, -4 volts for the binary input 100, -7 volts for the binary
input 111, and so on.
(with feedback resistor set at 800 ohms)
---------------------------------
j Binary j Output voltage j
---------------------------------
j 000 j 0.00 V j
---------------------------------
j 001 j -1.00 V j
---------------------------------
j 010 j -2.00 V j
---------------------------------
j 011 j -3.00 V j
---------------------------------
j 100 j -4.00 V j
---------------------------------
j 101 j -5.00 V j
---------------------------------
376 CHAPTER 13. DIGITAL-ANALOG CONVERSION
j 110 j -6.00 V j
---------------------------------
j 111 j -7.00 V j
---------------------------------
If we wish to expand the resolution of this DAC (add more bits to the input), all we need to do
is add more input resistors, holding to the same power-of-two sequence of values:
-
+
Vout
R
2R
4R
Binary
input
MSB
LSB
8R
16R
32R
Rfeedback
6-bit binary-weighted DAC
It should be noted that all logic gates must output exactly the same voltages when in the "high"
state. If one gate is outputting +5.02 volts for a "high" while another is outputting only +4.86
volts, the analog output of the DAC will be adversely a®ected. Likewise, all "low" voltage levels
should be identical between gates, ideally 0.00 volts exactly. It is recommended that CMOS output
gates are used, and that input/feedback resistor values are chosen so as to minimize the amount of
current each gate has to source or sink.
13.3 The R/2R DAC
An alternative to the binary-weighted-input DAC is the so-called R/2R DAC, which uses fewer
unique resistor values. A disadvantage of the former DAC design was its requirement of several
di®erent precise input resistor values: one unique value per binary input bit. Manufacture may be
simpli¯ed if there are fewer di®erent resistor values to purchase, stock, and sort prior to assembly.
Of course, we could take our last DAC circuit and modify it to use a single input resistance value,
by connecting multiple resistors together in series:
13.3. THE R/2R DAC 377
-
+
Vout
R
Binary
input
MSB
LSB
R R
R R R R
Unfortunately, this approach merely substitutes one type of complexity for another: volume of
components over diversity of component values. There is, however, a more e±cient design method-
ology.
By constructing a di®erent kind of resistor network on the input of our summing circuit, we can
achieve the same kind of binary weighting with only two kinds of resistor values, and with only a
modest increase in resistor count. This "ladder" network looks like this:
-
+
Vout
Binary
input
MSB
LSB
R R
2R 2R 2R
2R
R/2R "ladder" DAC
2R
Mathematically analyzing this ladder network is a bit more complex than for the previous circuit,
where each input resistor provided an easily-calculated gain for that bit. For those who are interested
in pursuing the intricacies of this circuit further, you may opt to use Thevenin's theorem for each
binary input (remember to consider the e®ects of the virtual ground), and/or use a simulation
program like SPICE to determine circuit response. Either way, you should obtain the following
table of ¯gures:
---------------------------------
j Binary j Output voltage j
---------------------------------
j 000 j 0.00 V j
---------------------------------
378 CHAPTER 13. DIGITAL-ANALOG CONVERSION
j 001 j -1.25 V j
---------------------------------
j 010 j -2.50 V j
---------------------------------
j 011 j -3.75 V j
---------------------------------
j 100 j -5.00 V j
---------------------------------
j 101 j -6.25 V j
---------------------------------
j 110 j -7.50 V j
---------------------------------
j 111 j -8.75 V j
---------------------------------
As was the case with the binary-weighted DAC design, we can modify the value of the feedback
resistor to obtain any "span" desired. For example, if we're using +5 volts for a "high" voltage level
and 0 volts for a "low" voltage level, we can obtain an analog output directly corresponding to the
binary input (011 = -3 volts, 101 = -5 volts, 111 = -7 volts, etc.) by using a feedback resistance
with a value of 1.6R instead of 2R.
13.4 Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of
a series of comparators, each one comparing the input signal to a unique reference voltage. The
comparator outputs connect to the inputs of a priority encoder circuit, which then produces a binary
output. The following illustration shows a 3-bit °ash ADC circuit:
13.4. FLASH ADC 379
Vref
R
R
R
R
R
R
R
R
-
+
Vin
8-line to
3-line
priority
encoder
Binary output
Vdd
+-
+-
+-
+-
+-
+-
+-
Vref is a stable reference voltage provided by a precision voltage regulator as part of the converter
circuit, not shown in the schematic. As the analog input voltage exceeds the reference voltage at
each comparator, the comparator outputs will sequentially saturate to a high state. The priority
encoder generates a binary number based on the highest-order active input, ignoring all other active
inputs.
When operated, the °ash ADC produces an output that looks something like this:
Time
Analog
input
Time
Digital
output
For this particular application, a regular priority encoder with all its inherent complexity isn't
necessary. Due to the nature of the sequential comparator output states (each comparator saturating
380 CHAPTER 13. DIGITAL-ANALOG CONVERSION
"high" in sequence from lowest to highest), the same "highest-order-input selection" e®ect may be
realized through a set of Exclusive-OR gates, allowing the use of a simpler, non-priority encoder:
Vref
R
R
R
R
R
R
R
R
-
+
Vin
8-line to
3-line
encoder
Binary output
Vdd +-
+-
+-
+-
+-
+-
+-
And, of course, the encoder circuit itself can be made from a matrix of diodes, demonstrating
just how simply this converter design may be constructed:
13.5. DIGITAL RAMP ADC 381
Vref
R
R
R
R
R
R
R
R
-
+
Vin
Binary output
7
6
5
4
3
2
1
Pulldown
resistors
+-
+-
+-
+-
+-
+-
Not only is the °ash converter the simplest in terms of operational theory, but it is the most
e±cient of the ADC technologies in terms of speed, being limited only in comparator and gate
propagation delays. Unfortunately, it is the most component-intensive for any given number of
output bits. This three-bit °ash ADC requires eight comparators. A four-bit version would require
16 comparators. With each additional output bit, the number of required comparators doubles.
Considering that eight bits is generally considered the minimum necessary for any practical ADC
(256 comparators needed!), the °ash methodology quickly shows its weakness.
An additional advantage of the °ash converter, often overlooked, is the ability for it to produce
a non-linear output. With equal-value resistors in the reference voltage divider network, each suc-
cessive binary count represents the same amount of analog signal increase, providing a proportional
response. For special applications, however, the resistor values in the divider network may be made
non-equal. This gives the ADC a custom, nonlinear response to the analog input signal. No other
ADC design is able to grant this signal-conditioning behavior with just a few component value
changes.
13.5 Digital ramp ADC
Also known as the stairstep-ramp, or simply counter A/D converter, this is also fairly easy to
understand but unfortunately su®ers from several limitations.
The basic idea is to connect the output of a free-running binary counter to the input of a DAC,
382 CHAPTER 13. DIGITAL-ANALOG CONVERSION
then compare the analog output of the DAC with the analog input signal to be digitized and use the
comparator's output to tell the counter when to stop counting and reset. The following schematic
shows the basic idea:
CTR
DAC
Vdd Vdd
Vdd
SRG
-
Vin +
Load
Binary
output
As the counter counts up with each clock pulse, the DAC outputs a slightly higher (more positive)
voltage. This voltage is compared against the input voltage by the comparator. If the input voltage
is greater than the DAC output, the comparator's output will be high and the counter will continue
counting normally. Eventually, though, the DAC output will exceed the input voltage, causing the
comparator's output to go low. This will cause two things to happen: ¯rst, the high-to-low transition
of the comparator's output will cause the shift register to "load" whatever binary count is being
output by the counter, thus updating the ADC circuit's output; secondly, the counter will receive a
low signal on the active-low LOAD input, causing it to reset to 00000000 on the next clock pulse.
The e®ect of this circuit is to produce a DAC output that ramps up to whatever level the analog
input signal is at, output the binary number corresponding to that level, and start over again.
Plotted over time, it looks like this:
13.6. SUCCESSIVE APPROXIMATION ADC 383
Time
Analog
input
Time
Digital
output
Note how the time between updates (new digital output values) changes depending on how high
the input voltage is. For low signal levels, the updates are rather close-spaced. For higher signal
levels, they are spaced further apart in time:
Digital
output
longer
time
shorter
time
For many ADC applications, this variation in update frequency (sample time) would not be
acceptable. This, and the fact that the circuit's need to count all the way from 0 at the beginning
of each count cycle makes for relatively slow sampling of the analog signal, places the digital-ramp
ADC at a disadvantage to other counter strategies.
13.6 Successive approximation ADC
One method of addressing the digital ramp ADC's shortcomings is the so-called successive-approximation
ADC. The only change in this design is a very special counter circuit known as a successive-
approximation register. Instead of counting up in binary sequence, this register counts by trying
all values of bits starting with the most-signi¯cant bit and ¯nishing at the least-signi¯cant bit.
Throughout the count process, the register monitors the comparator's output to see if the binary
count is less than or greater than the analog signal input, adjusting the bit values accordingly. The
way the register counts is identical to the "trial-and-¯t" method of decimal-to-binary conversion,
whereby di®erent values of bits are tried from MSB to LSB to get a binary number that equals
the original decimal number. The advantage to this counting strategy is much faster results: the
DAC output converges on the analog signal input in much larger steps than with the 0-to-full count
sequence of a regular counter.
Without showing the inner workings of the successive-approximation register (SAR), the circuit
looks like this:
384 CHAPTER 13. DIGITAL-ANALOG CONVERSION
DAC
Vdd Vdd
Vdd
SRG
-
Vin +
Binary
output
SAR
>/<
Done
It should be noted that the SAR is generally capable of outputting the binary number in serial
(one bit at a time) format, thus eliminating the need for a shift register. Plotted over time, the
operation of a successive-approximation ADC looks like this:
Time
Analog
input
Time
Digital
output
Note how the updates for this ADC occur at regular intervals, unlike the digital ramp ADC
circuit.
13.7. TRACKING ADC 385
13.7 Tracking ADC
A third variation on the counter-DAC-based converter theme is, in my estimation, the most elegant.
Instead of a regular "up" counter driving the DAC, this circuit uses an up/down counter. The counter
is continuously clocked, and the up/down control line is driven by the output of the comparator. So,
when the analog input signal exceeds the DAC output, the counter goes into the "count up" mode.
When the DAC output exceeds the analog input, the counter switches into the "count down" mode.
Either way, the DAC output always counts in the proper direction to track the input signal.
CTR
DAC
Vdd Vdd
-
Vin +
Binary
output
U/D
Notice how no shift register is needed to bu®er the binary count at the end of a cycle. Since the
counter's output continuously tracks the input (rather than counting to meet the input and then
resetting back to zero), the binary output is legitimately updated with every clock pulse.
An advantage of this converter circuit is speed, since the counter never has to reset. Note the
behavior of this circuit:
386 CHAPTER 13. DIGITAL-ANALOG CONVERSION
Time
Analog
input
Time
Digital
output
Note the much faster update time than any of the other "counting" ADC circuits. Also note
how at the very beginning of the plot where the counter had to "catch up" with the analog signal,
the rate of change for the output was identical to that of the ¯rst counting ADC. Also, with no shift
register in this circuit, the binary output would actually ramp up rather than jump from zero to an
accurate count as it did with the counter and successive approximation ADC circuits.
Perhaps the greatest drawback to this ADC design is the fact that the binary output is never
stable: it always switches between counts with every clock pulse, even with a perfectly stable analog
input signal. This phenomenon is informally known as bit bobble, and it can be problematic in some
digital systems.
This tendency can be overcome, though, through the creative use of a shift register. For example,
the counter's output may be latched through a parallel-in/parallel-out shift register only when the
output changes by two or more steps. Building a circuit to detect two or more successive counts in
the same direction takes a little ingenuity, but is worth the e®ort.
13.8 Slope (integrating) ADC
So far, we've only been able to escape the sheer volume of components in the °ash converter by
using a DAC as part of our ADC circuitry. However, this is not our only option. It is possible to
avoid using a DAC if we substitute an analog ramping circuit and a digital counter with precise
timing.
The is the basic idea behind the so-called single-slope, or integrating ADC. Instead of using a
DAC with a ramped output, we use an op-amp circuit called an integrator to generate a sawtooth
waveform which is then compared against the analog input by a comparator. The time it takes for
the sawtooth waveform to exceed the input signal voltage level is measured by means of a digital
counter clocked with a precise-frequency square wave (usually from a crystal oscillator). The basic
schematic diagram is shown here:
13.8. SLOPE (INTEGRATING) ADC 387
CTR
Vdd
-
+
Vin
Binary
output
-
+
-Vref CLR
Vdd
SRG
R C
The IGFET capacitor-discharging transistor scheme shown here is a bit oversimpli¯ed. In reality,
a latching circuit timed with the clock signal would most likely have to be connected to the IGFET
gate to ensure full discharge of the capacitor when the comparator's output goes high. The basic idea,
however, is evident in this diagram. When the comparator output is low (input voltage greater than
integrator output), the integrator is allowed to charge the capacitor in a linear fashion. Meanwhile,
the counter is counting up at a rate ¯xed by the precision clock frequency. The time it takes for the
capacitor to charge up to the same voltage level as the input depends on the input signal level and
the combination of -Vref , R, and C. When the capacitor reaches that voltage level, the comparator
output goes high, loading the counter's output into the shift register for a ¯nal output. The IGFET
is triggered "on" by the comparator's high output, discharging the capacitor back to zero volts.
When the integrator output voltage falls to zero, the comparator output switches back to a low
state, clearing the counter and enabling the integrator to ramp up voltage again.
This ADC circuit behaves very much like the digital ramp ADC, except that the comparator
reference voltage is a smooth sawtooth waveform rather than a "stairstep:"
Time
Analog
input
Time
Digital
output
The single-slope ADC su®ers all the disadvantages of the digital ramp ADC, with the added
drawback of calibration drift. The accurate correspondence of this ADC's output with its input is
dependent on the voltage slope of the integrator being matched to the counting rate of the counter
(the clock frequency). With the digital ramp ADC, the clock frequency had no e®ect on conversion
accuracy, only on update time. In this circuit, since the rate of integration and the rate of count
are independent of each other, variation between the two is inevitable as it ages, and will result in
388 CHAPTER 13. DIGITAL-ANALOG CONVERSION
a loss of accuracy. The only good thing to say about this circuit is that it avoids the use of a DAC,
which reduces circuit complexity.
An answer to this calibration drift dilemma is found in a design variation called the dual-slope
converter. In the dual-slope converter, an integrator circuit is driven positive and negative in alter-
nating cycles to ramp down and then up, rather than being reset to 0 volts at the end of every cycle.
In one direction of ramping, the integrator is driven by the positive analog input signal (producing
a negative, variable rate of output voltage change, or output slope) for a ¯xed amount of time, as
measured by a counter with a precision frequency clock. Then, in the other direction, with a ¯xed
reference voltage (producing a ¯xed rate of output voltage change) with time measured by the same
counter. The counter stops counting when the integrator's output reaches the same voltage as it was
when it started the ¯xed-time portion of the cycle. The amount of time it takes for the integrator's
capacitor to discharge back to its original output voltage, as measured by the magnitude accrued
by the counter, becomes the digital output of the ADC circuit.
The dual-slope method can be thought of analogously in terms of a rotary spring such as that
used in a mechanical clock mechanism. Imagine we were building a mechanism to measure the
rotary speed of a shaft. Thus, shaft speed is our "input signal" to be measured by this device. The
measurement cycle begins with the spring in a relaxed state. The spring is then turned, or "wound
up," by the rotating shaft (input signal) for a ¯xed amount of time. This places the spring in a
certain amount of tension proportional to the shaft speed: a greater shaft speed corresponds to a
faster rate of winding. and a greater amount of spring tension accumulated over that period of time.
After that, the spring is uncoupled from the shaft and allowed to unwind at a ¯xed rate, the time
for it to unwind back to a relaxed state measured by a timer device. The amount of time it takes
for the spring to unwind at that ¯xed rate will be directly proportional to the speed at which it was
wound (input signal magnitude) during the ¯xed-time portion of the cycle.
This technique of analog-to-digital conversion escapes the calibration drift problem of the single-
slope ADC because both the integrator's integration coe±cient (or "gain") and the counter's rate
of speed are in e®ect during the entire "winding" and "unwinding" cycle portions. If the counter's
clock speed were to suddenly increase, this would shorten the ¯xed time period where the integrator
"winds up" (resulting in a lesser voltage accumulated by the integrator), but it would also mean
that it would count faster during the period of time when the integrator was allowed to "unwind"
at a ¯xed rate. The proportion that the counter is counting faster will be the same proportion as
the integrator's accumulated voltage is diminished from before the clock speed change. Thus, the
clock speed error would cancel itself out and the digital output would be exactly what it should be.
Another important advantage of this method is that the input signal becomes averaged as it
drives the integrator during the ¯xed-time portion of the cycle. Any changes in the analog signal
during that period of time have a cumulative e®ect on the digital output at the end of that cycle.
Other ADC strategies merely "capture" the analog signal level at a single point in time every cycle.
If the analog signal is "noisy" (contains signi¯cant levels of spurious voltage spikes/dips), one of the
other ADC converter technologies may occasionally convert a spike or dip because it captures the
signal repeatedly at a single point in time. A dual-slope ADC, on the other hand, averages together
all the spikes and dips within the integration period, thus providing an output with greater noise
immunity. Dual-slope ADCs are used in applications demanding high accuracy.
13.9. DELTA-SIGMA (¢§) ADC 389
13.9 Delta-Sigma (¢§) ADC
One of the more advanced ADC technologies is the so-called delta-sigma, or ¢§ (using the proper
Greek letter notation). In mathematics and physics, the capital Greek letter delta (¢) represents
di®erence or change, while the capital letter sigma (§) represents summation: the adding of multiple
terms together. Sometimes this converter is referred to by the same Greek letters in reverse order:
sigma-delta, or §¢.
In a ¢§ converter, the analog input voltage signal is connected to the input of an integrator,
producing a voltage rate-of-change, or slope, at the output corresponding to input magnitude. This
ramping voltage is then compared against ground potential (0 volts) by a comparator. The compara-
tor acts as a sort of 1-bit ADC, producing 1 bit of output ("high" or "low") depending on whether
the integrator output is positive or negative. The comparator's output is then latched through a
D-type °ip-°op clocked at a high frequency, and fed back to another input channel on the integrator,
to drive the integrator in the direction of a 0 volt output. The basic circuit looks like this:
-
+
-
+
R
R
C
Vin
+V
-V
+V
-V
D
C
Q
Q
-
+
+V
-V
+V
Output
+V
The leftmost op-amp is the (summing) integrator. The next op-amp the integrator feeds into
is the comparator, or 1-bit ADC. Next comes the D-type °ip-°op, which latches the comparator's
output at every clock pulse, sending either a "high" or "low" signal to the next comparator at the
top of the circuit. This ¯nal comparator is necessary to convert the single-polarity 0V / 5V logic
level output voltage of the °ip-°op into a +V / -V voltage signal to be fed back to the integrator.
If the integrator output is positive, the ¯rst comparator will output a "high" signal to the D
input of the °ip-°op. At the next clock pulse, this "high" signal will be output from the Q line
into the noninverting input of the last comparator. This last comparator, seeing an input voltage
greater than the threshold voltage of 1/2 +V, saturates in a positive direction, sending a full +V
signal to the other input of the integrator. This +V feedback signal tends to drive the integrator
output in a negative direction. If that output voltage ever becomes negative, the feedback loop will
send a corrective signal (-V) back around to the top input of the integrator to drive it in a positive
direction. This is the delta-sigma concept in action: the ¯rst comparator senses a di®erence (¢)
390 CHAPTER 13. DIGITAL-ANALOG CONVERSION
between the integrator output and zero volts. The integrator sums (§) the comparator's output
with the analog input signal.
Functionally, this results in a serial stream of bits output by the °ip-°op. If the analog input
is zero volts, the integrator will have no tendency to ramp either positive or negative, except in
response to the feedback voltage. In this scenario, the °ip-°op output will continually oscillate
between "high" and "low," as the feedback system "hunts" back and forth, trying to maintain the
integrator output at zero volts:
Flip-flop output
Integrator output
0 1 0 1 0 1 0 1 0 1 0 1 0 1
DS converter operation with
0 volt analog input
If, however, we apply a negative analog input voltage, the integrator will have a tendency to
ramp its output in a positive direction. Feedback can only add to the integrator's ramping by a
¯xed voltage over a ¯xed time, and so the bit stream output by the °ip-°op will not be quite the
same:
Flip-flop output
Integrator output
0 1 0 1 0 1 0 1 0 1 0 1
DS converter operation with
1
small negative analog input
0
By applying a larger (negative) analog input signal to the integrator, we force its output to ramp
more steeply in the positive direction. Thus, the feedback system has to output more 1's than before
to bring the integrator output back to zero volts:
13.10. PRACTICAL CONSIDERATIONS OF ADC CIRCUITS 391
Flip-flop output
Integrator output
0 1 0 1 0 1
DS converter operation with
1 0 1 1 0 1 1 0
medium negative analog input
As the analog input signal increases in magnitude, so does the occurrence of 1's in the digital
output of the °ip-°op:
Flip-flop output
Integrator output
0 1 0 1 0 1
DS converter operation with
1 1 1 0 1 1 0 1
large negative analog input
A parallel binary number output is obtained from this circuit by averaging the serial stream of
bits together. For example, a counter circuit could be designed to collect the total number of 1's
output by the °ip-°op in a given number of clock pulses. This count would then be indicative of the
analog input voltage.
Variations on this theme exist, employing multiple integrator stages and/or comparator circuits
outputting more than 1 bit, but one concept common to all ¢§ converters is that of oversampling.
Oversampling is when multiple samples of an analog signal are taken by an ADC (in this case, a
1-bit ADC), and those digitized samples are averaged. The end result is an e®ective increase in the
number of bits resolved from the signal. In other words, an oversampled 1-bit ADC can do the same
job as an 8-bit ADC with one-time sampling, albeit at a slower rate.
13.10 Practical considerations of ADC circuits
Perhaps the most important consideration of an ADC is its resolution. Resolution is the number
of binary bits output by the converter. Because ADC circuits take in an analog signal, which is
continuously variable, and resolve it into one of many discrete steps, it is important to know how
many of these steps there are in total.
392 CHAPTER 13. DIGITAL-ANALOG CONVERSION
For example, an ADC with a 10-bit output can represent up to 1024 (210) unique conditions of
signal measurement. Over the range of measurement from 0% to 100%, there will be exactly 1024
unique binary numbers output by the converter (from 0000000000 to 1111111111, inclusive). An
11-bit ADC will have twice as many states to its output (2048, or 211), representing twice as many
unique conditions of signal measurement between 0% and 100%.
Resolution is very important in data acquisition systems (circuits designed to interpret and
record physical measurements in electronic form). Suppose we were measuring the height of water
in a 40-foot tall storage tank using an instrument with a 10-bit ADC. 0 feet of water in the tank
corresponds to 0% of measurement, while 40 feet of water in the tank corresponds to 100% of
measurement. Because the ADC is ¯xed at 10 bits of binary data output, it will interpret any given
tank level as one out of 1024 possible states. To determine how much physical water level will be
represented in each step of the ADC, we need to divide the 40 feet of measurement span by the
number of steps in the 0-to-1024 range of possibilities, which is 1023 (one less than 1024). Doing
this, we obtain a ¯gure of 0.039101 feet per step. This equates to 0.46921 inches per step, a little
less than half an inch of water level represented for every binary count of the ADC.
Water
tank
LT ADC 10-bit
output
0 ft
40 ft
20 ft
10 ft
30 ft
00000000002 = 0 feet of water level
11111111112 = 40 feet of water level
00000000012 = 0.039101 feet of water level
00000000102 = 0.07820 feet of water level
. . .
1 step
Binary output: Equivalent measurement:
1024 states
Level "transmitter"
A-to-D converter
This step value of 0.039101 feet (0.46921 inches) represents the smallest amount of tank level
change detectable by the instrument. Admittedly, this is a small amount, less than 0.1% of the
overall measurement span of 40 feet. However, for some applications it may not be ¯ne enough.
Suppose we needed this instrument to be able to indicate tank level changes down to one-tenth of
an inch. In order to achieve this degree of resolution and still maintain a measurement span of 40
feet, we would need an instrument with more than ten ADC bits.
To determine how many ADC bits are necessary, we need to ¯rst determine how many 1/10 inch
steps there are in 40 feet. The answer to this is 40/(0.1/12), or 4800 1/10 inch steps in 40 feet.
Thus, we need enough bits to provide at least 4800 discrete steps in a binary counting sequence. 10
bits gave us 1023 steps, and we knew this by calculating 2 to the power of 10 (210 = 1024) and then
subtracting one. Following the same mathematical procedure, 211-1 = 2047, 212-1 = 4095, and 213-1
= 8191. 12 bits falls shy of the amount needed for 4800 steps, while 13 bits is more than enough.
13.10. PRACTICAL CONSIDERATIONS OF ADC CIRCUITS 393
Therefore, we need an instrument with at least 13 bits of resolution.
Another important consideration of ADC circuitry is its sample frequency, or conversion rate.
This is simply the speed at which the converter outputs a new binary number. Like resolution,
this consideration is linked to the speci¯c application of the ADC. If the converter is being used
to measure slow-changing signals such as level in a water storage tank, it could probably have a
very slow sample frequency and still perform adequately. Conversely, if it is being used to digitize
an audio frequency signal cycling at several thousand times per second, the converter needs to be
considerably faster.
Consider the following illustration of ADC conversion rate versus signal type, typical of a
successive-approximation ADC with regular sample intervals:
Time
Sample times
Analog
input
Time
Digital
output
Here, for this slow-changing signal, the sample rate is more than adequate to capture its general
trend. But consider this example with the same sample time:
Time
Sample times
Analog
input
Time
Digital
output
When the sample period is too long (too slow), substantial details of the analog signal will be
missed. Notice how, especially in the latter portions of the analog signal, the digital output utterly
fails to reproduce the true shape. Even in the ¯rst section of the analog waveform, the digital
394 CHAPTER 13. DIGITAL-ANALOG CONVERSION
reproduction deviates substantially from the true shape of the wave.
It is imperative that an ADC's sample time is fast enough to capture essential changes in the
analog waveform. In data acquisition terminology, the highest-frequency waveform that an ADC
can theoretically capture is the so-called Nyquist frequency, equal to one-half of the ADC's sample
frequency. Therefore, if an ADC circuit has a sample frequency of 5000 Hz, the highest-frequency
waveform it can successfully resolve will be the Nyquist frequency of 2500 Hz.
If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist frequency
for that ADC, the converter will output a digitized signal of falsely low frequency. This phenomenon
is known as aliasing. Observe the following illustration to see how aliasing occurs:
Time
Sample times
Analog
input
Time
Digital
output
Aliasing
Note how the period of the output waveform is much longer (slower) than that of the input
waveform, and how the two waveform shapes aren't even similar:
Analog
input
Digital
output
Period
Period
It should be understood that the Nyquist frequency is an absolute maximum frequency limit
for an ADC, and does not represent the highest practical frequency measurable. To be safe, one
shouldn't expect an ADC to successfully resolve any frequency greater than one-¯fth to one-tenth
13.10. PRACTICAL CONSIDERATIONS OF ADC CIRCUITS 395
of its sample frequency.
A practical means of preventing aliasing is to place a low-pass ¯lter before the input of the ADC,
to block any signal frequencies greater than the practical limit. This way, the ADC circuitry will be
prevented from seeing any excessive frequencies and thus will not try to digitize them. It is generally
considered better that such frequencies go unconverted than to have them be "aliased" and appear
in the output as false signals.
Yet another measure of ADC performance is something called step recovery. This is a measure
of how quickly an ADC changes its output to match a large, sudden change in the analog input.
In some converter technologies especially, step recovery is a serious limitation. One example is
the tracking converter, which has a typically fast update period but a disproportionately slow step
recovery.
An ideal ADC has a great many bits for very ¯ne resolution, samples at lightning-fast speeds, and
recovers from steps instantly. It also, unfortunately, doesn't exist in the real world. Of course, any
of these traits may be improved through additional circuit complexity, either in terms of increased
component count and/or special circuit designs made to run at higher clock speeds. Di®erent ADC
technologies, though, have di®erent strengths. Here is a summary of them ranked from best to
worst:
Resolution/complexity ratio:
Single-slope integrating, dual-slope integrating, counter, tracking, successive approximation,
°ash.
Speed:
Flash, tracking, successive approximation, single-slope integrating & counter, dual-slope inte-
grating.
Step recovery:
Flash, successive-approximation, single-slope integrating & counter, dual-slope integrating, track-
ing.
Please bear in mind that the rankings of these di®erent ADC technologies depend on other
factors. For instance, how an ADC rates on step recovery depends on the nature of the step change.
A tracking ADC is equally slow to respond to all step changes, whereas a single-slope or counter
ADC will register a high-to-low step change quicker than a low-to-high step change. Successive-
approximation ADCs are almost equally fast at resolving any analog signal, but a tracking ADC will
consistently beat a successive-approximation ADC if the signal is changing slower than one resolution
step per clock pulse. I ranked integrating converters as having a greater resolution/complexity ratio
than counter converters, but this assumes that precision analog integrator circuits are less complex
to design and manufacture than precision DACs required within counter-based converters. Others
may not agree with this assumption.
396 CHAPTER 13. DIGITAL-ANALOG CONVERSION
Chapter 14
DIGITAL COMMUNICATION
Contents
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.2 Networks and busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
14.2.1 Short-distance busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
14.2.2 Extended-distance networks . . . . . . . . . . . . . . . . . . . . . . . . . . 404
14.3 Data °ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
14.4 Electrical signal types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
14.5 Optical data communication . . . . . . . . . . . . . . . . . . . . . . . . . 410
14.6 Network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
14.6.1 Point-to-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
14.6.2 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.6.3 Star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.6.4 Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.7 Network protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.8 Practical considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
14.1 Introduction
In the design of large and complex digital systems, it is often necessary to have one device commu-
nicate digital information to and from other devices. One advantage of digital information is that
it tends to be far more resistant to transmitted and interpreted errors than information symbol-
ized in an analog medium. This accounts for the clarity of digitally-encoded telephone connections,
compact audio disks, and for much of the enthusiasm in the engineering community for digital com-
munications technology. However, digital communication has its own unique pitfalls, and there are
multitudes of di®erent and incompatible ways in which it can be sent. Hopefully, this chapter will
enlighten you as to the basics of digital communication, its advantages, disadvantages, and practical
considerations.
397
398 CHAPTER 14. DIGITAL COMMUNICATION
Suppose we are given the task of remotely monitoring the level of a water storage tank. Our
job is to design a system to measure the level of water in the tank and send this information to a
distant location so that other people may monitor it. Measuring the tank's level is quite easy, and
can be accomplished with a number of di®erent types of instruments, such as °oat switches, pressure
transmitters, ultrasonic level detectors, capacitance probes, strain gauges, or radar level detectors.
For the sake of this illustration, we will use an analog level-measuring device with an output
signal of 4-20 mA. 4 mA represents a tank level of 0%, 20 mA represents a tank level of 100%,
and anything in between 4 and 20 mA represents a tank level proportionately between 0% and
100%. If we wanted to, we could simply send this 4-20 milliamp analog current signal to the remote
monitoring location by means of a pair of copper wires, where it would drive a panel meter of some
sort, the scale of which was calibrated to re°ect the depth of water in the tank, in whatever units
of measurement preferred.
Panel
meter
24 VDC
"Transmitter"
Water
tank
Analog tank-level measurement "loop"
This analog communication system would be simple and robust. For many applications, it would
su±ce for our needs perfectly. But, it is not the only way to get the job done. For the purposes of
exploring digital techniques, we'll explore other methods of monitoring this hypothetical tank, even
though the analog method just described might be the most practical.
The analog system, as simple as it may be, does have its limitations. One of them is the problem
of analog signal interference. Since the tank's water level is symbolized by the magnitude of DC
current in the circuit, any "noise" in this signal will be interpreted as a change in the water level.
With no noise, a plot of the current signal over time for a steady tank level of 50% would look like
this:
12 mA
0 mA
Time
Plot of signal at 50% tank level
If the wires of this circuit are arranged too close to wires carrying 60 Hz AC power, for exam-
14.1. INTRODUCTION 399
ple, inductive and capacitive coupling may create a false "noise" signal to be introduced into this
otherwise DC circuit. Although the low impedance of a 4-20 mA loop (250 ­, typically) means
that small noise voltages are signi¯cantly loaded (and thereby attenuated by the ine±ciency of the
capacitive/inductive coupling formed by the power wires), such noise can be signi¯cant enough to
cause measurement problems:
12 mA
0 mA
Time
Plot of signal at 50% tank level
(with 60 Hz interference)
The above example is a bit exaggerated, but the concept should be clear: any electrical noise
introduced into an analog measurement system will be interpreted as changes in the measured
quantity. One way to combat this problem is to symbolize the tank's water level by means of a
digital signal instead of an analog signal. We can do this really crudely by replacing the analog
transmitter device with a set of water level switches mounted at di®erent heights on the tank:
Water
tank
Tank level measurement with switches
L1 L2
Each of these switches is wired to close a circuit, sending current to individual lamps mounted
on a panel at the monitoring location. As each switch closed, its respective lamp would light, and
whoever looked at the panel would see a 5-lamp representation of the tank's level.
Being that each lamp circuit is digital in nature { either 100% on or 100% o® { electrical
interference from other wires along the run have much less e®ect on the accuracy of measurement
at the monitoring end than in the case of the analog signal. A huge amount of interference would
be required to cause an "o®" signal to be interpreted as an "on" signal, or vice versa. Relative
resistance to electrical interference is an advantage enjoyed by all forms of digital communication
over analog.
Now that we know digital signals are far more resistant to error induced by "noise," let's improve
on this tank level measurement system. For instance, we could increase the resolution of this tank
400 CHAPTER 14. DIGITAL COMMUNICATION
gauging system by adding more switches, for more precise determination of water level. Suppose
we install 16 switches along the tank's height instead of ¯ve. This would signi¯cantly improve our
measurement resolution, but at the expense of greatly increasing the quantity of wires needing to be
strung between the tank and the monitoring location. One way to reduce this wiring expense would
be to use a priority encoder to take the 16 switches and generate a binary number which represented
the same information:
16-line
to
4-line
priority
encoder
............
Q0 Q1 Q2 Q3
Q3Q2Q1Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Switch 0
Switch 15
Now, only 4 wires (plus any ground and power wires necessary) are needed to communicate the
information, as opposed to 16 wires (plus any ground and power wires). At the monitoring location,
we would need some kind of display device that could accept the 4-bit binary data and generate an
easy-to-read display for a person to view. A decoder, wired to accept the 4-bit data as its input
and light 1-of-16 output lamps, could be used for this task, or we could use a 4-bit decoder/driver
circuit to drive some kind of numerical digit display.
Still, a resolution of 1/16 tank height may not be good enough for our application. To better
resolve the water level, we need more bits in our binary output. We could add still more switches,
but this gets impractical rather quickly. A better option would be to re-attach our original analog
transmitter to the tank and electronically convert its 4-20 milliamp analog output into a binary
number with far more bits than would be practical using a set of discrete level switches. Since the
electrical noise we're trying to avoid is encountered along the long run of wire from the tank to the
monitoring location, this A/D conversion can take place at the tank (where we have a "clean" 4-20
mA signal). There are a variety of methods to convert an analog signal to digital, but we'll skip an
in-depth discussion of those techniques and concentrate on the digital signal communication itself.
The type of digital information being sent from our tank instrumentation to the monitoring
instrumentation is referred to as parallel digital data. That is, each binary bit is being sent along
its own dedicated wire, so that all bits arrive at their destination simultaneously. This obviously
necessitates the use of at least one wire per bit to communicate with the monitoring location. We
could further reduce our wiring needs by sending the binary data along a single channel (one wire
+ ground), so that each bit is communicated one at a time. This type of information is referred to
as serial digital data.
We could use a multiplexer or a shift register to take the parallel data from the A/D converter (at
the tank transmitter), and convert it to serial data. At the receiving end (the monitoring location)
14.2. NETWORKS AND BUSSES 401
we could use a demultiplexer or another shift register to convert the serial data to parallel again
for use in the display circuitry. The exact details of how the mux/demux or shift register pairs are
maintained in synchronization is, like A/D conversion, a topic for another lesson. Fortunately, there
are digital IC chips called UARTs (Universal Asynchronous Receiver-Transmitters) that handle all
these details on their own and make the designer's life much simpler. For now, we must continue to
focus our attention on the matter at hand: how to communicate the digital information from the
tank to the monitoring location.
14.2 Networks and busses
This collection of wires that I keep referring to between the tank and the monitoring location can
be called a bus or a network. The distinction between these two terms is more semantic than
technical, and the two may be used interchangeably for all practical purposes. In my experience, the
term "bus" is usually used in reference to a set of wires connecting digital components within the
enclosure of a computer device, and "network" is for something that is physically more widespread.
In recent years, however, the word "bus" has gained popularity in describing networks that specialize
in interconnecting discrete instrumentation sensors over long distances ("Fieldbus" and "Pro¯bus"
are two examples). In either case, we are making reference to the means by which two or more
digital devices are connected together so that data can be communicated between them.
Names like "Fieldbus" or "Pro¯bus" encompass not only the physical wiring of the bus or net-
work, but also the speci¯ed voltage levels for communication, their timing sequences (especially
for serial data transmission), connector pinout speci¯cations, and all other distinguishing technical
features of the network. In other words, when we speak of a certain type of bus or network by
name, we're actually speaking of a communications standard, roughly analogous to the rules and
vocabulary of a written language. For example, before two or more people can become pen-pals,
they must be able to write to one another in a common format. To merely have a mail system that
is able to deliver their letters to each other is not enough. If they agree to write to each other in
French, they agree to hold to the conventions of character set, vocabulary, spelling, and grammar
that is speci¯ed by the standard of the French language. Likewise, if we connect two Pro¯bus devices
together, they will be able to communicate with each other only because the Pro¯bus standard has
speci¯ed such important details as voltage levels, timing sequences, etc. Simply having a set of
wires strung between multiple devices is not enough to construct a working system (especially if the
devices were built by di®erent manufacturers!).
To illustrate in detail, let's design our own bus standard. Taking the crude water tank measure-
ment system with ¯ve switches to detect varying levels of water, and using (at least) ¯ve wires to
conduct the signals to their destination, we can lay the foundation for the mighty BogusBus:
402 CHAPTER 14. DIGITAL COMMUNICATION
Water
tank
BogusBusTM
LS
LS
LS
LS
LS
1
2
3
4
5 LS5
LS4
LS3
LS2
LS1
24 V 24 V
5 5
4 4
3 3
2 2
1 1
+V +V
-V -V
Lamp
5
Lamp
Lamp
Lamp
Lamp
4
3
2
1
Connector
The physical wiring for the BogusBus consists of seven wires between the transmitter device
(switches) and the receiver device (lamps). The transmitter consists of all components and wiring
connections to the left of the leftmost connectors (the "{>>{" symbols). Each connector symbol
represents a complementary male and female element. The bus wiring consists of the seven wires
between the connector pairs. Finally, the receiver and all of its constituent wiring lies to the right of
the rightmost connectors. Five of the network wires (labeled 1 through 5) carry the data while two of
those wires (labeled +V and -V) provide connections for DC power supplies. There is a standard for
the 7-pin connector plugs, as well. The pin layout is asymmetrical to prevent "backward" connection.
In order for manufacturers to receive the awe-inspiring "BogusBus-compliant" certi¯cation on
their products, they would have to comply with the speci¯cations set by the designers of BogusBus
(most likely another company, which designed the bus for a speci¯c task and ended up marketing
it for a wide variety of purposes). For instance, all devices must be able to use the 24 Volt DC
supply power of BogusBus: the switch contacts in the transmitter must be rated for switching
that DC voltage, the lamps must de¯nitely be rated for being powered by that voltage, and the
connectors must be able to handle it all. Wiring, of course, must be in compliance with that same
standard: lamps 1 through 5, for example, must be wired to the appropriate pins so that when LS4
of Manufacturer XYZ's transmitter closes, lamp 4 of Manufacturer ABC's receiver lights up, and so
on. Since both transmitter and receiver contain DC power supplies rated at an output of 24 Volts,
all transmitter/receiver combinations (from all certi¯ed manufacturers) must have power supplies
that can be safely wired in parallel. Consider what could happen if Manufacturer XYZ made a
transmitter with the negative (-) side of their 24VDC power supply attached to earth ground and
Manufacturer ABC made a receiver with the positive (+) side of their 24VDC power supply attached
to earth ground. If both earth grounds are relatively "solid" (that is, a low resistance between them,
such as might be the case if the two grounds were made on the metal structure of an industrial
building), the two power supplies would short-circuit each other!
14.2. NETWORKS AND BUSSES 403
BogusBus, of course, is a completely hypothetical and very impractical example of a digital
network. It has incredibly poor data resolution, requires substantial wiring to connect devices, and
communicates in only a single direction (from transmitter to receiver). It does, however, su±ce as
a tutorial example of what a network is and some of the considerations associated with network
selection and operation.
There are many types of buses and networks that you might come across in your profession. Each
one has its own applications, advantages, and disadvantages. It is worthwhile to associate yourself
with some of the "alphabet soup" that is used to label the various designs:
14.2.1 Short-distance busses
PC/AT Bus used in early IBM-compatible computers to connect peripheral devices such as disk
drive and sound cards to the motherboard of the computer.
PCI Another bus used in personal computers, but not limited to IBM-compatibles. Much faster
than PC/AT. Typical data transfer rate of 100 Mbytes/second (32 bit) and 200 Mbytes/second (64
bit).
PCMCIA A bus designed to connect peripherals to laptop and notebook sized personal com-
puters. Has a very small physical "footprint," but is considerably slower than other popular PC
buses.
VME A high-performance bus (co-designed by Motorola, and based on Motorola's earlier Versa-
Bus standard) for constructing versatile industrial and military computers, where multiple memory,
peripheral, and even microprocessor cards could be plugged in to a passive "rack" or "card cage" to
facilitate custom system designs. Typical data transfer rate of 50 Mbytes/second (64 bits wide).
VXI Actually an expansion of the VME bus, VXI (VME eXtension for Instrumentation) includes
the standard VME bus along with connectors for analog signals between cards in the rack.
S-100 Sometimes called the Altair bus, this bus standard was the product of a conference in
1976, intended to serve as an interface to the Intel 8080 microprocessor chip. Similar in philosophy
to the VME, where multiple function cards could be plugged in to a passive "rack," facilitating the
construction of custom systems.
MC6800 The Motorola equivalent of the Intel-centric S-100 bus, designed to interface peripheral
devices to the popular Motorola 6800 microprocessor chip.
STD Stands for Simple-To-Design, and is yet another passive "rack" similar to the PC/AT bus,
and lends itself well toward designs based on IBM-compatible hardware. Designed by Pro-Log, it is
8 bits wide (parallel), accommodating relatively small (4.5 inch by 6.5 inch) circuit cards.
Multibus I and II Another bus intended for the °exible design of custom computer systems,
designed by Intel. 16 bits wide (parallel).
CompactPCI An industrial adaptation of the personal computer PCI standard, designed as a
higher-performance alternative to the older VME bus. At a bus clock speed of 66 MHz, data transfer
rates are 200 Mbytes/ second (32 bit) or 400 Mbytes/sec (64 bit).
Microchannel Yet another bus, this one designed by IBM for their ill-fated PS/2 series of
computers, intended for the interfacing of PC motherboards to peripheral devices.
IDE A bus used primarily for connecting personal computer hard disk drives with the appropriate
peripheral cards. Widely used in today's personal computers for hard drive and CD-ROM drive
interfacing.
SCSI An alternative (technically superior to IDE) bus used for personal computer disk drives.
SCSI stands for Small Computer System Interface. Used in some IBM-compatible PC's, as well
404 CHAPTER 14. DIGITAL COMMUNICATION
as Macintosh (Apple), and many mini and mainframe business computers. Used to interface hard
drives, CD-ROM drives, °oppy disk drives, printers, scanners, modems, and a host of other peripheral
devices. Speeds up to 1.5 Mbytes per second for the original standard.
GPIB (IEEE 488) General Purpose Interface Bus, also known as HPIB or IEEE 488, which
was intended for the interfacing of electronic test equipment such as oscilloscopes and multimeters
to personal computers. 8 bit wide address/data "path" with 8 additional lines for communications
control.
Centronics parallel Widely used on personal computers for interfacing printer and plotter
devices. Sometimes used to interface with other peripheral devices, such as external ZIP (100 Mbyte
°oppy) disk drives and tape drives.
USB Universal Serial Bus, which is intended to interconnect many external peripheral devices
(such as keyboards, modems, mice, etc.) to personal computers. Long used on Macintosh PC's, it
is now being installed as new equipment on IBM-compatible machines.
FireWire (IEEE 1394) A high-speed serial network capable of operating at 100, 200, or 400
Mbps with versatile features such as "hot swapping" (adding or removing devices with the power
on) and °exible topology. Designed for high-performance personal computer interfacing.
Bluetooth A radio-based communications network designed for o±ce linking of computer de-
vices. Provisions for data security designed into this network standard.
14.2.2 Extended-distance networks
20 mA current loop Not to be confused with the common instrumentation 4-20 mA analog
standard, this is a digital communications network based on interrupting a 20 mA (or sometimes 60
mA) current loop to represent binary data. Although the low impedance gives good noise immunity,
it is susceptible to wiring faults (such as breaks) which would fail the entire network.
RS-232C The most common serial network used in computer systems, often used to link pe-
ripheral devices such as printers and mice to a personal computer. Limited in speed and distance
(typically 45 feet and 20 kbps, although higher speeds can be run with shorter distances). I've been
able to run RS-232 reliably at speeds in excess of 100 kbps, but this was using a cable only 6 feet
long! RS-232C is often referred to simply as RS-232 (no "C").
RS-422A/RS-485 Two serial networks designed to overcome some of the distance and versa-
tility limitations of RS-232C. Used widely in industry to link serial devices together in electrically
"noisy" plant environments. Much greater distance and speed limitations than RS-232C, typically
over half a mile and at speeds approaching 10 Mbps.
Ethernet (IEEE 802.3) A high-speed network which links computers and some types of pe-
ripheral devices together. "Normal" Ethernet runs at a speed of 10 million bits/second, and "Fast"
Ethernet runs at 100 million bits/second. The slower (10 Mbps) Ethernet has been implemented
in a variety of means on copper wire (thick coax = "10BASE5", thin coax = "10BASE2", twisted-
pair = "10BASE-T"), radio, and on optical ¯ber ("10BASE-F"). The Fast Ethernet has also been
implemented on a few di®erent means (twisted-pair, 2 pair = 100BASE-TX; twisted-pair, 4 pair =
100BASE-T4; optical ¯ber = 100BASE-FX).
Token ring Another high-speed network linking computer devices together, using a philosophy
of communication that is much di®erent from Ethernet, allowing for more precise response times
from individual network devices, and greater immunity to network wiring damage.
FDDI A very high-speed network exclusively implemented on ¯ber-optic cabling.
14.3. DATA FLOW 405
Modbus/Modbus Plus Originally implemented by the Modicon corporation, a large maker of
Programmable Logic Controllers (PLCs) for linking remote I/O (Input/Output) racks with a PLC
processor. Still quite popular.
Pro¯bus Originally implemented by the Siemens corporation, another large maker of PLC
equipment.
Foundation Fieldbus A high-performance bus expressly designed to allow multiple process
instruments (transmitters, controllers, valve positioners) to communicate with host computers and
with each other. May ultimately displace the 4-20 mA analog signal as the standard means of
interconnecting process control instrumentation in the future.
14.3 Data °ow
Buses and networks are designed to allow communication to occur between individual devices that
are interconnected. The °ow of information, or data, between nodes can take a variety of forms:
Transmitter Receiver
Simplex communication
With simplex communication, all data °ow is unidirectional: from the designated transmitter to
the designated receiver. BogusBus is an example of simplex communication, where the transmitter
sent information to the remote monitoring location, but no information is ever sent back to the water
tank. If all we want to do is send information one-way, then simplex is just ¯ne. Most applications,
however, demand more:
Duplex communication
Receiver /
Transmitter Transmitter
Receiver /
With duplex communication, the °ow of information is bidirectional for each device. Duplex can
be further divided into two sub-categories:
406 CHAPTER 14. DIGITAL COMMUNICATION
Receiver /
Transmitter Transmitter
Receiver /
Half-duplex
Transmitter
Receiver
Receiver
Transmitter
Full-duplex
(take turns)
(simultaneous)
Half-duplex communication may be likened to two tin cans on the ends of a single taut string:
Either can may be used to transmit or receive, but not at the same time. Full-duplex communication
is more like a true telephone, where two people can talk at the same time and hear one another
simultaneously, the mouthpiece of one phone transmitting the the earpiece of the other, and vice
versa. Full-duplex is often facilitated through the use of two separate channels or networks, with an
individual set of wires for each direction of communication. It is sometimes accomplished by means
of multiple-frequency carrier waves, especially in radio links, where one frequency is reserved for
each direction of communication.
14.4 Electrical signal types
With BogusBus, our signals were very simple and straightforward: each signal wire (1 through 5)
carried a single bit of digital data, 0 Volts representing "o®" and 24 Volts DC representing "on."
Because all the bits arrived at their destination simultaneously, we would call BogusBus a parallel
network technology. If we were to improve the performance of BogusBus by adding binary encoding
(to the transmitter end) and decoding (to the receiver end), so that more steps of resolution were
available with fewer wires, it would still be a parallel network. If, however, we were to add a parallel-
to-serial converter at the transmitter end and a serial-to-parallel converter at the receiver end, we
would have something quite di®erent.
It is primarily with the use of serial technology that we are forced to invent clever ways to transmit
data bits. Because serial data requires us to send all data bits through the same wiring channel from
transmitter to receiver, it necessitates a potentially high frequency signal on the network wiring.
Consider the following illustration: a modi¯ed BogusBus system is communicating digital data in
parallel, binary-encoded form. Instead of 5 discrete bits like the original BogusBus, we're sending
8 bits from transmitter to receiver. The A/D converter on the transmitter side generates a new
output every second. That makes for 8 bits per second of data being sent to the receiver. For the
sake of illustration, let's say that the transmitter is bouncing between an output of 10101010 and
10101011 every update (once per second):
14.4. ELECTRICAL SIGNAL TYPES 407
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1 second
Since only the least signi¯cant bit (Bit 1) is changing, the frequency on that wire (to ground) is
only 1/2 Hertz. In fact, no matter what numbers are being generated by the A/D converter between
updates, the frequency on any wire in this modi¯ed BogusBus network cannot exceed 1/2 Hertz,
because that's how fast the A/D updates its digital output. 1/2 Hertz is pretty slow, and should
present no problems for our network wiring.
On the other hand, if we used an 8-bit serial network, all data bits must appear on the single
channel in sequence. And these bits must be output by the transmitter within the 1-second window
of time between A/D converter updates. Therefore, the alternating digital output of 10101010 and
10101011 (once per second) would look something like this:
1 second
Serial data
10101010
10101011
10101010
10101011
The frequency of our BogusBus signal is now approximately 4 Hertz instead of 1/2 Hertz, an
eightfold increase! While 4 Hertz is still fairly slow, and does not constitute an engineering problem,
you should be able to appreciate what might happen if we were transmitting 32 or 64 bits of data
per update, along with the other bits necessary for parity checking and signal synchronization, at
an update rate of thousands of times per second! Serial data network frequencies start to enter the
radio range, and simple wires begin to act as antennas, pairs of wires as transmission lines, with all
their associated quirks due to inductive and capacitive reactances.
What is worse, the signals that we're trying to communicate along a serial network are of a square-
wave shape, being binary bits of information. Square waves are peculiar things, being mathematically
equivalent to an in¯nite series of sine waves of diminishing amplitude and increasing frequency. A
simple square wave at 10 kHz is actually "seen" by the capacitance and inductance of the network
as a series of multiple sine-wave frequencies which extend into the hundreds of kHz at signi¯cant
amplitudes. What we receive at the other end of a long 2-conductor network won't look like a clean
square wave anymore, even under the best of conditions!
When engineers speak of network bandwidth, they're referring to the practical frequency limit of
a network medium. In serial communication, bandwidth is a product of data volume (binary bits
408 CHAPTER 14. DIGITAL COMMUNICATION
per transmitted "word") and data speed ("words" per second). The standard measure of network
bandwidth is bits per second, or bps. An obsolete unit of bandwidth known as the baud is sometimes
falsely equated with bits per second, but is actually the measure of signal level changes per second.
Many serial network standards use multiple voltage or current level changes to represent a single
bit, and so for these applications bps and baud are not equivalent.
The general BogusBus design, where all bits are voltages referenced to a common "ground" con-
nection, is the worst-case situation for high-frequency square wave data communication. Everything
will work well for short distances, where inductive and capacitive e®ects can be held to a minimum,
but for long distances this method will surely be problematic:
Input
Signal
Output
Signal
Transmitter Receiver
signal wire
ground wire
Stray capacitance
Ground-referenced voltage signal
A robust alternative to the common ground signal method is the di®erential voltage method,
where each bit is represented by the di®erence of voltage between a ground-isolated pair of wires,
instead of a voltage between one wire and a common ground. This tends to limit the capacitive
and inductive e®ects imposed upon each signal and the tendency for the signals to be corrupted due
to outside electrical interference, thereby signi¯cantly improving the practical distance of a serial
network:
Input
Signal
Output
Signal
Transmitter Receiver
signal wire
Differential voltage signal
signal wire
Both signal wires isolated
from ground!
diminishing effect.
Capacitance through ground
minimized due to series-
The triangular ampli¯er symbols represent di®erential ampli¯ers, which output a voltage signal
between two wires, neither one electrically common with ground. Having eliminated any relation
between the voltage signal and ground, the only signi¯cant capacitance imposed on the signal voltage
is that existing between the two signal wires. Capacitance between a signal wire and a grounded
conductor is of much less e®ect, because the capacitive path between the two signal wires via a
14.4. ELECTRICAL SIGNAL TYPES 409
ground connection is two capacitances in series (from signal wire #1 to ground, then from ground to
signal wire #2), and series capacitance values are always less than any of the individual capacitances.
Furthermore, any "noise" voltage induced between the signal wires and earth ground by an external
source will be ignored, because that noise voltage will likely be induced on both signal wires in equal
measure, and the receiving ampli¯er only responds to the di®erential voltage between the two signal
wires, rather than the voltage between any one of them and earth ground.
RS-232C is a prime example of a ground-referenced serial network, while RS-422A is a prime
example of a di®erential voltage serial network. RS-232C ¯nds popular application in o±ce en-
vironments where there is little electrical interference and wiring distances are short. RS-422A is
more widely used in industrial applications where longer wiring distances and greater potential for
electrical interference from AC power wiring exists.
However, a large part of the problem with digital network signals is the square-wave nature of such
voltages, as was previously mentioned. If only we could avoid square waves all together, we could
avoid many of their inherent di±culties in long, high-frequency networks. One way of doing this is
to modulate a sine wave voltage signal with our digital data. "Modulation" means that magnitude
of one signal has control over some aspect of another signal. Radio technology has incorporated
modulation for decades now, in allowing an audio-frequency voltage signal to control either the
amplitude (AM) or frequency (FM) of a much higher frequency "carrier" voltage, which is then send
to the antenna for transmission. The frequency-modulation (FM) technique has found more use in
digital networks than amplitude-modulation (AM), except that it's referred to as Frequency Shift
Keying (FSK). With simple FSK, sine waves of two distinct frequencies are used to represent the
two binary states, 1 and 0:
0 (low)
1 (high)
0 (low)
Due to the practical problems of getting the low/high frequency sine waves to begin and end at
the zero crossover points for any given combination of 0's and 1's, a variation of FSK called phase-
continuous FSK is sometimes used, where the consecutive combination of a low/high frequency
represents one binary state and the combination of a high/low frequency represents the other. This
also makes for a situation where each bit, whether it be 0 or 1, takes exactly the same amount of
time to transmit along the network:
0 (low) 1 (high)
With sine wave signal voltages, many of the problems encountered with square wave digital
signals are minimized, although the circuitry required to modulate (and demodulate) the network
signals is more complex and expensive.
410 CHAPTER 14. DIGITAL COMMUNICATION
14.5 Optical data communication
A modern alternative to sending (binary) digital information via electric voltage signals is to use
optical (light) signals. Electrical signals from digital circuits (high/low voltages) may be converted
into discrete optical signals (light or no light) with LEDs or solid-state lasers. Likewise, light signals
can be translated back into electrical form through the use of photodiodes or phototransistors for
introduction into the inputs of gate circuits.
Transmitter Receiver
Light pulses
Transmitting digital information in optical form may be done in open air, simply by aiming a laser
at a photodetector at a remote distance, but interference with the beam in the form of temperature
inversion layers, dust, rain, fog, and other obstructions can present signi¯cant engineering problems:
Transmitter Receiver
Interference
One way to avoid the problems of open-air optical data transmission is to send the light pulses
down an ultra-pure glass ¯ber. Glass ¯bers will "conduct" a beam of light much as a copper wire
will conduct electrons, with the advantage of completely avoiding all the associated problems of
inductance, capacitance, and external interference plaguing electrical signals. Optical ¯bers keep
the light beam contained within the ¯ber core by a phenomenon known as total internal re°ectance.
An optical ¯ber is composed of two layers of ultra-pure glass, each layer made of glass with a
slightly di®erent refractive index, or capacity to "bend" light. With one type of glass concentrically
layered around a central glass core, light introduced into the central core cannot escape outside the
¯ber, but is con¯ned to travel within the core:
14.5. OPTICAL DATA COMMUNICATION 411
Cladding
Cladding
Core
Light
These layers of glass are very thin, the outer "cladding" typically 125 microns (1 micron = 1
millionth of a meter, or 10¡6 meter) in diameter. This thinness gives the ¯ber considerable °exibility.
To protect the ¯ber from physical damage, it is usually given a thin plastic coating, placed inside of
a plastic tube, wrapped with kevlar ¯bers for tensile strength, and given an outer sheath of plastic
similar to electrical wire insulation. Like electrical wires, optical ¯bers are often bundled together
within the same sheath to form a single cable.
Optical ¯bers exceed the data-handling performance of copper wire in almost every regard. They
are totally immune to electromagnetic interference and have very high bandwidths. However, they
are not without certain weaknesses.
One weakness of optical ¯ber is a phenomenon known as microbending. This is where the ¯ber
is bend around too small of a radius, causing light to escape the inner core, through the cladding:
Escaping
light
Reflected
light
Sharp
bend
Microbending
Not only does microbending lead to diminished signal strength due to the lost light, but it also
constitutes a security weakness in that a light sensor intentionally placed on the outside of a sharp
bend could intercept digital data transmitted over the ¯ber.
Another problem unique to optical ¯ber is signal distortion due to multiple light paths, or modes,
412 CHAPTER 14. DIGITAL COMMUNICATION
having di®erent distances over the length of the ¯ber. When light is emitted by a source, the photons
(light particles) do not all travel the exact same path. This fact is patently obvious in any source
of light not conforming to a straight beam, but is true even in devices such as lasers. If the optical
¯ber core is large enough in diameter, it will support multiple pathways for photons to travel, each
of these pathways having a slightly di®erent length from one end of the ¯ber to the other. This type
of optical ¯ber is called multimode ¯ber:
Light
"Modes" of light traveling in a fiber
A light pulse emitted by the LED taking a shorter path through the ¯ber will arrive at the
detector sooner than light pulses taking longer paths. The result is distortion of the square-wave's
rising and falling edges, called pulse stretching. This problem becomes worse as the overall ¯ber
length is increased:
Transmitted
pulse
Received
pulse
"Pulse-stretching" in optical fiber
However, if the ¯ber core is made small enough (around 5 microns in diameter), light modes are
restricted to a single pathway with one length. Fiber so designed to permit only a single mode of light
is known as single-mode ¯ber. Because single-mode ¯ber escapes the problem of pulse stretching
experienced in long cables, it is the ¯ber of choice for long-distance (several miles or more) networks.
The drawback, of course, is that with only one mode of light, single-mode ¯bers do not conduct as
as much light as multimode ¯bers. Over long distances, this exacerbates the need for "repeater"
units to boost light power.
14.6 Network topology
If we want to connect two digital devices with a network, we would have a kind of network known
as "point-to-point:"
Device
1
Device
2
Network
Point-to-Point topology
14.6. NETWORK TOPOLOGY 413
For the sake of simplicity, the network wiring is symbolized as a single line between the two
devices. In actuality, it may be a twisted pair of wires, a coaxial cable, an optical ¯ber, or even
a seven-conductor BogusBus. Right now, we're merely focusing on the "shape" of the network,
technically known as its topology.
If we want to include more devices (sometimes called nodes) on this network, we have several
options of network con¯guration to choose from:
Device
1
Device
2
Bus topology
Device Device
3 4
Device
1
Device
2
Device Device
3 4
Star topology Hub
Device
1
Device
2
Device Device
3 4
Ring topology
Many network standards dictate the type of topology which is used, while others are more
versatile. Ethernet, for example, is commonly implemented in a "bus" topology but can also be
implemented in a "star" or "ring" topology with the appropriate interconnecting equipment. Other
networks, such as RS-232C, are almost exclusively point-to-point; and token ring (as you might have
guessed) is implemented solely in a ring topology.
Di®erent topologies have di®erent pros and cons associated with them:
14.6.1 Point-to-point
Quite obviously the only choice for two nodes.
414 CHAPTER 14. DIGITAL COMMUNICATION
14.6.2 Bus
Very simple to install and maintain. Nodes can be easily added or removed with minimal wiring
changes. On the other hand, the one bus network must handle all communication signals from all
nodes. This is known as broadcast networking, and is analogous to a group of people talking to each
other over a single telephone connection, where only one person can talk at a time (limiting data
exchange rates), and everyone can hear everyone else when they talk (which can be a data security
issue). Also, a break in the bus wiring can lead to nodes being isolated in groups.
14.6.3 Star
With devices known as "gateways" at branching points in the network, data °ow can be restricted
between nodes, allowing for private communication between speci¯c groups of nodes. This addresses
some of the speed and security issues of the simple bus topology. However, those branches could
easily be cut o® from the rest of the "star" network if one of the gateways were to fail. Can also be
implemented with "switches" to connect individual nodes to a larger network on demand. Such a
switched network is similar to the standard telephone system.
14.6.4 Ring
This topology provides the best reliability with the least amount of wiring. Since each node has two
connection points to the ring, a single break in any part of the ring doesn't a®ect the integrity of
the network. The devices, however, must be designed with this topology in mind. Also, the network
must be interrupted to install or remove nodes. As with bus topology, ring networks are broadcast
by nature.
As you might suspect, two or more ring topologies may be combined to give the "best of both
worlds" in a particular application. Quite often, industrial networks end up in this fashion over
time, simply from engineers and technicians joining multiple networks together for the bene¯t of
plant-wide information access.
14.7 Network protocols
Aside from the issues of the physical network (signal types and voltage levels, connector pinouts,
cabling, topology, etc.), there needs to be a standardized way in which communication is arbitrated
between multiple nodes in a network, even if it's as simple as a two-node, point-to-point system.
When a node "talks" on the network, it is generating a signal on the network wiring, be it high
and low DC voltage levels, some kind of modulated AC carrier wave signal, or even pulses of light
in a ¯ber. Nodes that "listen" are simply measuring that applied signal on the network (from the
transmitting node) and passively monitoring it. If two or more nodes "talk" at the same time,
however, their output signals may clash (imagine two logic gates trying to apply opposite signal
voltages to a single line on a bus!), corrupting the transmitted data.
The standardized method by which nodes are allowed to transmit to the bus or network wiring
is called a protocol. There are many di®erent protocols for arbitrating the use of a common network
between multiple nodes, and I'll cover just a few here. However, it's good to be aware of these
few, and to understand why some work better for some purposes than others. Usually, a speci¯c
14.7. NETWORK PROTOCOLS 415
protocol is associated with a standardized type of network. This is merely another "layer" to the
set of standards which are speci¯ed under the titles of various networks.
The International Standards Organization (ISO) has speci¯ed a general architecture of network
speci¯cations in their DIS7498 model (applicable to most any digital network). Consisting of seven
"layers," this outline attempts to categorize all levels of abstraction necessary to communicate digital
data.
² Level 1: Physical Speci¯es electrical and mechanical details of communication: wire type,
connector design, signal types and levels.
² Level 2: Data link De¯nes formats of messages, how data is to be addressed, and error
detection/correction techniques.
² Level 3: Network Establishes procedures for encapsulation of data into "packets" for trans-
mission and reception.
² Level 4: Transport Among other things, the transport layer de¯nes how complete data ¯les
are to be handled over a network.
² Level 5: Session Organizes data transfer in terms of beginning and end of a speci¯c trans-
mission. Analogous to job control on a multitasking computer operating system.
² Level 6: Presentation Includes de¯nitions for character sets, terminal control, and graphics
commands so that abstract data can be readily encoded and decoded between communicating
devices.
² Level 7: Application The end-user standards for generating and/or interpreting communi-
cated data in its ¯nal form. In other words, the actual computer programs using the commu-
nicated data.
Some established network protocols only cover one or a few of the DIS7498 levels. For example,
the widely used RS-232C serial communications protocol really only addresses the ¯rst ("physical")
layer of this seven-layer model. Other protocols, such as the X-windows graphical client/server
system developed at MIT for distributed graphic-user-interface computer systems, cover all seven
layers.
Di®erent protocols may use the same physical layer standard. An example of this is the RS-
422A and RS-485 protocols, both of which use the same di®erential-voltage transmitter and receiver
circuitry, using the same voltage levels to denote binary 1's and 0's. On a physical level, these two
communication protocols are identical. However, on a more abstract level the protocols are di®erent:
RS-422A is point-to-point only, while RS-485 supports a bus topology "multidrop" with up to 32
addressable nodes.
Perhaps the simplest type of protocol is the one where there is only one transmitter, and all
the other nodes are merely receivers. Such is the case for BogusBus, where a single transmitter
generates the voltage signals impressed on the network wiring, and one or more receiver units (with
5 lamps each) light up in accord with the transmitter's output. This is always the case with a
simplex network: there's only one talker, and everyone else listens!
When we have multiple transmitting nodes, we must orchestrate their transmissions in such a
way that they don't con°ict with one another. Nodes shouldn't be allowed to talk when another
416 CHAPTER 14. DIGITAL COMMUNICATION
node is talking, so we give each node the ability to "listen" and to refrain from talking until the
network is silent. This basic approach is called Carrier Sense Multiple Access (CSMA), and there
exists a few variations on this theme. Please note that CSMA is not a standardized protocol in
itself, but rather a methodology that certain protocols follow.
One variation is to simply let any node begin to talk as soon as the network is silent. This is
analogous to a group of people meeting at a round table: anyone has the ability to start talking, so
long as they don't interrupt anyone else. As soon as the last person stops talking, the next person
waiting to talk will begin. So, what happens when two or more people start talking at once? In a
network, the simultaneous transmission of two or more nodes is called a collision. With CSMA/CD
(CSMA/Collision Detection), the nodes that collide simply reset themselves with a random delay
timer circuit, and the ¯rst one to ¯nish its time delay tries to talk again. This is the basic protocol
for the popular Ethernet network.
Another variation of CSMA is CSMA/BA (CSMA/Bitwise Arbitration), where colliding nodes
refer to pre-set priority numbers which dictate which one has permission to speak ¯rst. In other
words, each node has a "rank" which settles any dispute over who gets to start talking ¯rst after
a collision occurs, much like a group of people where dignitaries and common citizens are mixed.
If a collision occurs, the dignitary is generally allowed to speak ¯rst and the common person waits
afterward.
In either of the two examples above (CSMA/CD and CSMA/BA), we assumed that any node
could initiate a conversation so long as the network was silent. This is referred to as the "unsolicited"
mode of communication. There is a variation called "solicited" mode for either CSMA/CD or
CSMA/BA where the initial transmission is only allowed to occur when a designated master node
requests (solicits) a reply. Collision detection (CD) or bitwise arbitration (BA) applies only to
post-collision arbitration as multiple nodes respond to the master device's request.
An entirely di®erent strategy for node communication is the Master/Slave protocol, where a
single master device allots time slots for all the other nodes on the network to transmit, and schedules
these time slots so that multiple nodes cannot collide. The master device addresses each node by
name, one at a time, letting that node talk for a certain amount of time. When it is ¯nished, the
master addresses the next node, and so on, and so on.
Yet another strategy is the Token-Passing protocol, where each node gets a turn to talk (one at
a time), and then grants permission for the next node to talk when it's done. Permission to talk is
passed around from node to node as each one hands o® the "token" to the next in sequential order.
The token itself is not a physical thing: it is a series of binary 1's and 0's broadcast on the network,
carrying a speci¯c address of the next node permitted to talk. Although token-passing protocol is
often associated with ring-topology networks, it is not restricted to any topology in particular. And
when this protocol is implemented in a ring network, the sequence of token passing does not have
to follow the physical connection sequence of the ring.
Just as with topologies, multiple protocols may be joined together over di®erent segments of
a heterogeneous network, for maximum bene¯t. For instance, a dedicated Master/Slave network
connecting instruments together on the manufacturing plant °oor may be linked through a gateway
device to an Ethernet network which links multiple desktop computer workstations together, one of
those computer workstations acting as a gateway to link the data to an FDDI ¯ber network back to
the plant's mainframe computer. Each network type, topology, and protocol serves di®erent needs
and applications best, but through gateway devices, they can all share the same data.
It is also possible to blend multiple protocol strategies into a new hybrid within a single network
type. Such is the case for Foundation Fieldbus, which combines Master/Slave with a form of token-
14.8. PRACTICAL CONSIDERATIONS 417
passing. A Link Active Scheduler (LAS) device sends scheduled "Compel Data" (CD) commands
to query slave devices on the Fieldbus for time-critical information. In this regard, Fieldbus is a
Master/Slave protocol. However, when there's time between CD queries, the LAS sends out "tokens"
to each of the other devices on the Fieldbus, one at a time, giving them opportunity to transmit
any unscheduled data. When those devices are done transmitting their information, they return
the token back to the LAS. The LAS also probes for new devices on the Fieldbus with a "Probe
Node" (PN) message, which is expected to produce a "Probe Response" (PR) back to the LAS.
The responses of devices back to the LAS, whether by PR message or returned token, dictate their
standing on a "Live List" database which the LAS maintains. Proper operation of the LAS device
is absolutely critical to the functioning of the Fieldbus, so there are provisions for redundant LAS
operation by assigning "Link Master" status to some of the nodes, empowering them to become
alternate Link Active Schedulers if the operating LAS fails.
Other data communications protocols exist, but these are the most popular. I had the oppor-
tunity to work on an old (circa 1975) industrial control system made by Honeywell where a master
device called the Highway Tra±c Director, or HTD, arbitrated all network communications. What
made this network interesting is that the signal sent from the HTD to all slave devices for permitting
transmission was not communicated on the network wiring itself, but rather on sets of individual
twisted-pair cables connecting the HTD with each slave device. Devices on the network were then
divided into two categories: those nodes connected to the HTD which were allowed to initiate trans-
mission, and those nodes not connected to the HTD which could only transmit in response to a
query sent by one of the former nodes. Primitive and slow are the only ¯tting adjectives for this
communication network scheme, but it functioned adequately for its time.
14.8 Practical considerations
A principal consideration for industrial control networks, where the monitoring and control of real-
life processes must often occur quickly and at set times, is the guaranteed maximum communication
time from one node to another. If you're controlling the position of a nuclear reactor coolant valve
with a digital network, you need to be able to guarantee that the valve's network node will receive
the proper positioning signals from the control computer at the right times. If not, very bad things
could happen!
The ability for a network to guarantee data "throughput" is called determinism. A deterministic
network has a guaranteed maximum time delay for data transfer from node to node, whereas a
non-deterministic network does not. The preeminent example of a non-deterministic network is
Ethernet, where the nodes rely on random time-delay circuits to reset and re-attempt transmission
after a collision. Being that a node's transmission of data could be delayed inde¯nitely from a long
series of re-sets and re-tries after repeated collisions, there is no guarantee that its data will ever
get sent out to the network. Realistically though, the odds are so astronomically great that such a
thing would happen that it is of little practical concern in a lightly-loaded network.
Another important consideration, especially for industrial control networks, is network fault
tolerance: that is, how susceptible is a particular network's signaling, topology, and/or protocol
to failures? We've already brie°y discussed some of the issues surrounding topology, but protocol
impacts reliability just as much. For example, a Master/Slave network, while being extremely
deterministic (a good thing for critical controls), is entirely dependent upon the master node to keep
everything going (generally a bad thing for critical controls). If the master node fails for any reason,
418 CHAPTER 14. DIGITAL COMMUNICATION
none of the other nodes will be able to transmit any data at all, because they'll never receive their
alloted time slot permissions to do so, and the whole system will fail.
A similar issue surrounds token-passing systems: what happens if the node holding the token
were to fail before passing the token on to the next node? Some token-passing systems address this
possibility by having a few designated nodes generate a new token if the network is silent for too
long. This works ¯ne if a node holding the token dies, but it causes problems if part of a network
falls silent because a cable connection comes undone: the portion of the network that falls silent
generates its own token after awhile, and you essentially are left with two smaller networks with
one token that's getting passed around each of them to sustain communication. Trouble occurs,
however, if that cable connection gets plugged back in: those two segmented networks are joined
in to one again, and now there's two tokens being passed around one network, resulting in nodes'
transmissions colliding!
There is no "perfect network" for all applications. The task of the engineer and technician is to
know the application and know the operations of the network(s) available. Only then can e±cient
system design and maintenance become a reality.
Chapter 15
DIGITAL STORAGE (MEMORY)
Contents
15.1 Why digital? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.2 Digital memory terms and concepts . . . . . . . . . . . . . . . . . . . . 420
15.3 Modern nonmechanical memory . . . . . . . . . . . . . . . . . . . . . . 422
15.4 Historical, nonmechanical memory technologies . . . . . . . . . . . . . 424
15.5 Read-only memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
15.6 Memory with moving parts: "Drives" . . . . . . . . . . . . . . . . . . . 430
15.1 Why digital?
Although many textbooks provide good introductions to digital memory technology, I intend to make
this chapter unique in presenting both past and present technologies to some degree of detail. While
many of these memory designs are obsolete, their foundational principles are still quite interesting
and educational, and may even ¯nd re-application in the memory technologies of the future.
The basic goal of digital memory is to provide a means to store and access binary data: sequences
of 1's and 0's. The digital storage of information holds advantages over analog techniques much the
same as digital communication of information holds advantages over analog communication. This
is not to say that digital data storage is unequivocally superior to analog, but it does address
some of the more common problems associated with analog techniques and thus ¯nds immense
popularity in both consumer and industrial applications. Digital data storage also complements
digital computation technology well, and thus ¯nds natural application in the world of computers.
The most evident advantage of digital data storage is the resistance to corruption. Suppose
that we were going to store a piece of data regarding the magnitude of a voltage signal by means
of magnetizing a small chunk of magnetic material. Since many magnetic materials retain their
strength of magnetization very well over time, this would be a logical media candidate for long-term
storage of this particular data (in fact, this is precisely how audio and video tape technology works:
thin plastic tape is impregnated with particles of iron-oxide material, which can be magnetized or
demagnetized via the application of a magnetic ¯eld from an electromagnet coil. The data is then
419
420 CHAPTER 15. DIGITAL STORAGE (MEMORY)
retrieved from the tape by moving the magnetized tape past another coil of wire, the magnetized
spots on the tape inducing voltage in that coil, reproducing the voltage waveform initially used to
magnetize the tape).
If we represent an analog signal by the strength of magnetization on spots of the tape, the storage
of data on the tape will be susceptible to the smallest degree of degradation of that magnetization.
As the tape ages and the magnetization fades, the analog signal magnitude represented on the tape
will appear to be less than what it was when we ¯rst recorded the data. Also, if any spurious
magnetic ¯elds happen to alter the magnetization on the tape, even if it's only by a small amount,
that altering of ¯eld strength will be interpreted upon re-play as an altering (or corruption) of the
signal that was recorded. Since analog signals have in¯nite resolution, the smallest degree of change
will have an impact on the integrity of the data storage.
If we were to use that same tape and store the data in binary digital form, however, the strength
of magnetization on the tape would fall into two discrete levels: "high" and "low," with no valid
in-between states. As the tape aged or was exposed to spurious magnetic ¯elds, those same locations
on the tape would experience slight alteration of magnetic ¯eld strength, but unless the alterations
were extreme, no data corruption would occur upon re-play of the tape. By reducing the resolution
of the signal impressed upon the magnetic tape, we've gained signi¯cant immunity to the kind
of degradation and "noise" typically plaguing stored analog data. On the other hand, our data
resolution would be limited to the scanning rate and the number of bits output by the A/D converter
which interpreted the original analog signal, so the reproduction wouldn't necessarily be "better"
than with analog, merely more rugged. With the advanced technology of modern A/D's, though,
the tradeo® is acceptable for most applications.
Also, by encoding di®erent types of data into speci¯c binary number schemes, digital storage
allows us to archive a wide variety of information that is often di±cult to encode in analog form. Text,
for example, is represented quite easily with the binary ASCII code, seven bits for each character,
including punctuation marks, spaces, and carriage returns. A wider range of text is encoded using
the Unicode standard, in like manner. Any kind of numerical data can be represented using binary
notation on digital media, and any kind of information that can be encoded in numerical form (which
almost any kind can!) is storable, too. Techniques such as parity and checksum error detection can
be employed to further guard against data corruption, in ways that analog does not lend itself to.
15.2 Digital memory terms and concepts
When we store information in some kind of circuit or device, we not only need some way to store and
retrieve it, but also to locate precisely where in the device that it is. Most, if not all, memory devices
can be thought of as a series of mail boxes, folders in a ¯le cabinet, or some other metaphor where
information can be located in a variety of places. When we refer to the actual information being
stored in the memory device, we usually refer to it as the data. The location of this data within the
storage device is typically called the address, in a manner reminiscent of the postal service.
With some types of memory devices, the address in which certain data is stored can be called up
by means of parallel data lines in a digital circuit (we'll discuss this in more detail later in this lesson).
With other types of devices, data is addressed in terms of an actual physical location on the surface of
some type of media (the tracks and sectors of circular computer disks, for instance). However, some
memory devices such as magnetic tapes have a one-dimensional type of data addressing: if you want
to play your favorite song in the middle of a cassette tape album, you have to fast-forward to that
15.2. DIGITAL MEMORY TERMS AND CONCEPTS 421
spot in the tape, arriving at the proper spot by means of trial-and-error, judging the approximate
area by means of a counter that keeps track of tape position, and/or by the amount of time it takes to
get there from the beginning of the tape. The access of data from a storage device falls roughly into
two categories: random access and sequential access. Random access means that you can quickly
and precisely address a speci¯c data location within the device, and non-random simply means that
you cannot. A vinyl record platter is an example of a random-access device: to skip to any song,
you just position the stylus arm at whatever location on the record that you want (compact audio
disks so the same thing, only they do it automatically for you). Cassette tape, on the other hand, is
sequential. You have to wait to go past the other songs in sequence before you can access or address
the song that you want to skip to.
The process of storing a piece of data to a memory device is called writing, and the process of
retrieving data is called reading. Memory devices allowing both reading and writing are equipped
with a way to distinguish between the two tasks, so that no mistake is made by the user (writing
new information to a device when all you wanted to do is see what was stored there). Some devices
do not allow for the writing of new data, and are purchased "pre-written" from the manufacturer.
Such is the case for vinyl records and compact audio disks, and this is typically referred to in the
digital world as read-only memory, or ROM. Cassette audio and video tape, on the other hand, can
be re-recorded (re-written) or purchased blank and recorded fresh by the user. This is often called
read-write memory.
Another distinction to be made for any particular memory technology is its volatility, or data
storage permanence without power. Many electronic memory devices store binary data by means
of circuits that are either latched in a "high" or "low" state, and this latching e®ect holds only as
long as electric power is maintained to those circuits. Such memory would be properly referred to as
volatile. Storage media such as magnetized disk or tape is nonvolatile, because no source of power is
needed to maintain data storage. This is often confusing for new students of computer technology,
because the volatile electronic memory typically used for the construction of computer devices is
commonly and distinctly referred to as RAM (Random Access Memory). While RAM memory
is typically randomly-accessed, so is virtually every other kind of memory device in the computer!
What "RAM" really refers to is the volatility of the memory, and not its mode of access. Nonvolatile
memory integrated circuits in personal computers are commonly (and properly) referred to as ROM
(Read-Only Memory), but their data contents are accessed randomly, just like the volatile memory
circuits!
Finally, there needs to be a way to denote how much data can be stored by any particular memory
device. This, fortunately for us, is very simple and straightforward: just count up the number of
bits (or bytes, 1 byte = 8 bits) of total data storage space. Due to the high capacity of modern
data storage devices, metric pre¯xes are generally a±xed to the unit of bytes in order to represent
storage space: 1.6 Gigabytes is equal to 1.6 billion bytes, or 12.8 billion bits, of data storage capacity.
The only caveat here is to be aware of rounded numbers. Because the storage mechanisms of many
random-access memory devices are typically arranged so that the number of "cells" in which bits
of data can be stored appears in binary progression (powers of 2), a "one kilobyte" memory device
most likely contains 1024 (2 to the power of 10) locations for data bytes rather than exactly 1000.
A "64 kbyte" memory device actually holds 65,536 bytes of data (2 to the 16th power), and should
probably be called a "66 Kbyte" device to be more precise. When we round numbers in our base-10
system, we fall out of step with the round equivalents in the base-2 system.
422 CHAPTER 15. DIGITAL STORAGE (MEMORY)
15.3 Modern nonmechanical memory
Now we can proceed to studying speci¯c types of digital storage devices. To start, I want to explore
some of the technologies which do not require any moving parts. These are not necessarily the newest
technologies, as one might suspect, although they will most likely replace moving-part technologies
in the future.
A very simple type of electronic memory is the bistable multivibrator. Capable of storing a single
bit of data, it is volatile (requiring power to maintain its memory) and very fast. The D-latch is
probably the simplest implementation of a bistable multivibrator for memory usage, the D input
serving as the data "write" input, the Q output serving as the "read" output, and the enable input
serving as the read/write control line:
Q
D Q
E
Data write Data read
Write/Read
If we desire more than one bit's worth of storage (and we probably do), we'll have to have many
latches arranged in some kind of an array where we can selectively address which one (or which set)
we're reading from or writing to. Using a pair of tristate bu®ers, we can connect both the data
write input and the data read output to a common data bus line, and enable those bu®ers to either
connect the Q output to the data line (READ), connect the D input to the data line (WRITE), or
keep both bu®ers in the High-Z state to disconnect D and Q from the data line (unaddressed mode).
One memory "cell" would look like this, internally:
Q
D Q
E
Write/Read
Memory cell circuit
Enable
Address
Data
in/out
15.3. MODERN NONMECHANICAL MEMORY 423
When the address enable input is 0, both tristate bu®ers will be placed in high-Z mode, and the
latch will be disconnected from the data input/output (bus) line. Only when the address enable
input is active (1) will the latch be connected to the data bus. Every latch circuit, of course, will
be enabled with a di®erent "address enable" (AE) input line, which will come from a 1-of-n output
decoder:
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
AE Data
W/R
4-line to
16-line
decoder
A0 A1
A3
A2
AE
W/R
Data
Memory cell 15
Memory cell 0
....
. . .
. . .
. . .
. . .
. . .
1-bit
data
bus
cell 14
cell 13
cell 12
cell 3
cell 2
cell 1
.
.
.
.
.
.
16 x 1 bit memory
Write/Read
In the above circuit, 16 memory cells are individually addressed with a 4-bit binary code input
into the decoder. If a cell is not addressed, it will be disconnected from the 1-bit data bus by its
internal tristate bu®ers: consequently, data cannot be either written or read through the bus to or
from that cell. Only the cell circuit that is addressed by the 4-bit decoder input will be accessible
through the data bus.
This simple memory circuit is random-access and volatile. Technically, it is known as a static
RAM. Its total memory capacity is 16 bits. Since it contains 16 addresses and has a data bus that
is 1 bit wide, it would be designated as a 16 x 1 bit static RAM circuit. As you can see, it takes an
incredible number of gates (and multiple transistors per gate!) to construct a practical static RAM
circuit. This makes the static RAM a relatively low-density device, with less capacity than most
other types of RAM technology per unit IC chip space. Because each cell circuit consumes a certain
amount of power, the overall power consumption for a large array of cells can be quite high. Early
static RAM banks in personal computers consumed a fair amount of power and generated a lot of
heat, too. CMOS IC technology has made it possible to lower the speci¯c power consumption of
static RAM circuits, but low storage density is still an issue.
To address this, engineers turned to the capacitor instead of the bistable multivibrator as a
means of storing binary data. A tiny capacitor could serve as a memory cell, complete with a
single MOSFET transistor for connecting it to the data bus for charging (writing a 1), discharging
(writing a 0), or reading. Unfortunately, such tiny capacitors have very small capacitances, and their
charge tends to "leak" away through any circuit impedances quite rapidly. To combat this tendency,
engineers designed circuits internal to the RAM memory chip which would periodically read all cells
424 CHAPTER 15. DIGITAL STORAGE (MEMORY)
and recharge (or "refresh") the capacitors as needed. Although this added to the complexity of the
circuit, it still required far less componentry than a RAM built of multivibrators. They called this
type of memory circuit a dynamic RAM, because of its need of periodic refreshing.
Recent advances in IC chip manufacturing has led to the introduction of °ash memory, which
works on a capacitive storage principle like the dynamic RAM, but uses the insulated gate of a
MOSFET as the capacitor itself.
Before the advent of transistors (especially the MOSFET), engineers had to implement digital
circuitry with gates constructed from vacuum tubes. As you can imagine, the enormous comparative
size and power consumption of a vacuum tube as compared to a transistor made memory circuits
like static and dynamic RAM a practical impossibility. Other, rather ingenious, techniques to store
digital data without the use of moving parts were developed.
15.4 Historical, nonmechanical memory technologies
Perhaps the most ingenious technique was that of the delay line. A delay line is any kind of device
which delays the propagation of a pulse or wave signal. If you've ever heard a sound echo back and
forth through a canyon or cave, you've experienced an audio delay line: the noise wave travels at
the speed of sound, bouncing o® of walls and reversing direction of travel. The delay line "stores"
data on a very temporary basis if the signal is not strengthened periodically, but the very fact that
it stores data at all is a phenomenon exploitable for memory technology.
Early computer delay lines used long tubes ¯lled with liquid mercury, which was used as the
physical medium through which sound waves traveled along the length of the tube. An electri-
cal/sound transducer was mounted at each end, one to create sound waves from electrical impulses,
and the other to generate electrical impulses from sound waves. A stream of serial binary data was
sent to the transmitting transducer as a voltage signal. The sequence of sound waves would travel
from left to right through the mercury in the tube and be received by the transducer at the other
end. The receiving transducer would receive the pulses in the same order as they were transmitted:
Mercury
-
+
-
+
Amplifier Data pulses moving at speed of sound Amplifier
Data pulses moving at speed of light
Mercury tube delay-line memory
A feedback circuit connected to the receiving transducer would drive the transmitting transducer
again, sending the same sequence of pulses through the tube as sound waves, storing the data as
long as the feedback circuit continued to function. The delay line functioned like a ¯rst-in-¯rst-out
(FIFO) shift register, and external feedback turned that shift register behavior into a ring counter,
cycling the bits around inde¯nitely.
The delay line concept su®ered numerous limitations from the materials and technology that were
then available. The EDVAC computer of the early 1950's used 128 mercury-¯lled tubes, each one
about 5 feet long and storing a maximum of 384 bits. Temperature changes would a®ect the speed
15.4. HISTORICAL, NONMECHANICAL MEMORY TECHNOLOGIES 425
of sound in the mercury, thus skewing the time delay in each tube and causing timing problems.
Later designs replaced the liquid mercury medium with solid rods of glass, quartz, or special metal
that delayed torsional (twisting) waves rather than longitudinal (lengthwise) waves, and operated
at much higher frequencies.
One such delay line used a special nickel-iron-titanium wire (chosen for its good temperature
stability) about 95 feet in length, coiled to reduce the overall package size. The total delay time
from one end of the wire to the other was about 9.8 milliseconds, and the highest practical clock
frequency was 1 MHz. This meant that approximately 9800 bits of data could be stored in the
delay line wire at any given time. Given di®erent means of delaying signals which wouldn't be so
susceptible to environmental variables (such as serial pulses of light within a long optical ¯ber), this
approach might someday ¯nd re-application.
Another approach experimented with by early computer engineers was the use of a cathode ray
tube (CRT), the type commonly used for oscilloscope, radar, and television viewscreens, to store
binary data. Normally, the focused and directed electron beam in a CRT would be used to make
bits of phosphor chemical on the inside of the tube glow, thus producing a viewable image on the
screen. In this application, however, the desired result was the creation of an electric charge on the
glass of the screen by the impact of the electron beam, which would then be detected by a metal
grid placed directly in front of the CRT. Like the delay line, the so-called Williams Tube memory
needed to be periodically refreshed with external circuitry to retain its data. Unlike the delay line
mechanisms, it was virtually immune to the environmental factors of temperature and vibration.
The IBM model 701 computer sported a Williams Tube memory with 4 Kilobyte capacity and a
bad habit of "overcharging" bits on the tube screen with successive re-writes so that false "1" states
might over°ow to adjacent spots on the screen.
The next major advance in computer memory came when engineers turned to magnetic materials
as a means of storing binary data. It was discovered that certain compounds of iron, namely "ferrite,"
possessed hysteresis curves that were almost square:
Field intensity (H)
Flux density
(B)
Hysteresis curve for ferrite
Shown on a graph with the strength of the applied magnetic ¯eld on the horizontal axis (¯eld
intensity), and the actual magnetization (orientation of electron spins in the ferrite material) on
426 CHAPTER 15. DIGITAL STORAGE (MEMORY)
the vertical axis (°ux density), ferrite won't become magnetized one direction until the applied ¯eld
exceeds a critical threshold value. Once that critical value is exceeded, the electrons in the ferrite
"snap" into magnetic alignment and the ferrite becomes magnetized. If the applied ¯eld is then
turned o®, the ferrite maintains full magnetism. To magnetize the ferrite in the other direction
(polarity), the applied magnetic ¯eld must exceed the critical value in the opposite direction. Once
that critical value is exceeded, the electrons in the ferrite "snap" into magnetic alignment in the
opposite direction. Once again, if the applied ¯eld is then turned o®, the ferrite maintains full
magnetism. To put it simply, the magnetization of a piece of ferrite is "bistable."
Exploiting this strange property of ferrite, we can use this natural magnetic "latch" to store a
binary bit of data. To set or reset this "latch," we can use electric current through a wire or coil
to generate the necessary magnetic ¯eld, which will then be applied to the ferrite. Jay Forrester of
MIT applied this principle in inventing the magnetic "core" memory, which became the dominant
computer memory technology during the 1970's.
. . . . . . . . . . . .
............
Column wire drivers
Row
wire
drivers
8 x 8
magnetic
core memory
array
A grid of wires, electrically insulated from one another, crossed through the center of many
ferrite rings, each of which being called a "core." As DC current moved through any wire from the
power supply to ground, a circular magnetic ¯eld was generated around that energized wire. The
resistor values were set so that the amount of current at the regulated power supply voltage would
produce slightly more than 1/2 the critical magnetic ¯eld strength needed to magnetize any one of
the ferrite rings. Therefore, if column #4 wire was energized, all the cores on that column would
be subjected to the magnetic ¯eld from that one wire, but it would not be strong enough to change
the magnetization of any of those cores. However, if column #4 wire and row #5 wire were both
energized, the core at that intersection of column #4 and row #5 would be subjected to a sum
of those two magnetic ¯elds: a magnitude strong enough to "set" or "reset" the magnetization of
that core. In other words, each core was addressed by the intersection of row and column. The
15.4. HISTORICAL, NONMECHANICAL MEMORY TECHNOLOGIES 427
distinction between "set" and "reset" was the direction of the core's magnetic polarity, and that bit
value of data would be determined by the polarity of the voltages (with respect to ground) that the
row and column wires would be energized with.
The following photograph shows a core memory board from a Data General brand, "Nova"
model computer, circa late 1960's or early 1970's. It had a total storage capacity of 4 kbytes (that's
kilobytes, not megabytes!). A ball-point pen is shown for size comparison:
The electronic components seen around the periphery of this board are used for "driving" the
column and row wires with current, and also to read the status of a core. A close-up photograph
reveals the ring-shaped cores, through which the matrix wires thread. Again, a ball-point pen is
shown for size comparison:
A core memory board of later design (circa 1971) is shown in the next photograph. Its cores
are much smaller and more densely packed, giving more memory storage capacity than the former
board (8 kbytes instead of 4 kbytes):
428 CHAPTER 15. DIGITAL STORAGE (MEMORY)
And, another close-up of the cores:
Writing data to core memory was easy enough, but reading that data was a bit of a trick. To
facilitate this essential function, a "read" wire was threaded through all the cores in a memory
matrix, one end of it being grounded and the other end connected to an ampli¯er circuit. A pulse
of voltage would be generated on this "read" wire if the addressed core changed states (from 0 to
1, or 1 to 0). In other words, to read a core's value, you had to write either a 1 or a 0 to that core
and monitor the voltage induced on the read wire to see if the core changed. Obviously, if the core's
state was changed, you would have to re-set it back to its original state, or else the data would have
been lost. This process is known as a destructive read, because data may be changed (destroyed) as
it is read. Thus, refreshing is necessary with core memory, although not in every case (that is, in
the case of the core's state not changing when either a 1 or a 0 was written to it).
One major advantage of core memory over delay lines and Williams Tubes was nonvolatility.
The ferrite cores maintained their magnetization inde¯nitely, with no power or refreshing required.
It was also relatively easy to build, denser, and physically more rugged than any of its predecessors.
Core memory was used from the 1960's until the late 1970's in many computer systems, including
the computers used for the Apollo space program, CNC machine tool control computers, business
("mainframe") computers, and industrial control systems. Despite the fact that core memory is long
obsolete, the term "core" is still used sometimes with reference to a computer's RAM memory.
All the while that delay lines, Williams Tube, and core memory technologies were being invented,
the simple static RAM was being improved with smaller active component (vacuum tube or tran-
15.5. READ-ONLY MEMORY 429
sistor) technology. Static RAM was never totally eclipsed by its competitors: even the old ENIAC
computer of the 1950's used vacuum tube ring-counter circuitry for data registers and computation.
Eventually though, smaller and smaller scale IC chip manufacturing technology gave transistors the
practical edge over other technologies, and core memory became a museum piece in the 1980's.
One last attempt at a magnetic memory better than core was the bubble memory. Bubble
memory took advantage of a peculiar phenomenon in a mineral called garnet, which, when arranged
in a thin ¯lm and exposed to a constant magnetic ¯eld perpendicular to the ¯lm, supported tiny
regions of oppositely-magnetized "bubbles" that could be nudged along the ¯lm by prodding with
other external magnetic ¯elds. "Tracks" could be laid on the garnet to focus the movement of the
bubbles by depositing magnetic material on the surface of the ¯lm. A continuous track was formed
on the garnet which gave the bubbles a long loop in which to travel, and motive force was applied
to the bubbles with a pair of wire coils wrapped around the garnet and energized with a 2-phase
voltage. Bubbles could be created or destroyed with a tiny coil of wire strategically placed in the
bubbles' path.
The presence of a bubble represented a binary "1" and the absence of a bubble represented a
binary "0." Data could be read and written in this chain of moving magnetic bubbles as they passed
by the tiny coil of wire, much the same as the read/write "head" in a cassette tape player, reading
the magnetization of the tape as it moves. Like core memory, bubble memory was nonvolatile: a
permanent magnet supplied the necessary background ¯eld needed to support the bubbles when
the power was turned o®. Unlike core memory, however, bubble memory had phenomenal storage
density: millions of bits could be stored on a chip of garnet only a couple of square inches in
size. What killed bubble memory as a viable alternative to static and dynamic RAM was its slow,
sequential data access. Being nothing more than an incredibly long serial shift register (ring counter),
access to any particular portion of data in the serial string could be quite slow compared to other
memory technologies.
An electrostatic equivalent of the bubble memory is the Charge-Coupled Device (CCD) memory,
an adaptation of the CCD devices used in digital photography. Like bubble memory, the bits are
serially shifted along channels on the substrate material by clock pulses. Unlike bubble memory,
the electrostatic charges decay and must be refreshed. CCD memory is therefore volatile, with high
storage density and sequential access. Interesting, isn't it? The old Williams Tube memory was
adapted from CRT viewing technology, and CCD memory from video recording technology.
15.5 Read-only memory
Read-only memory (ROM) is similar in design to static or dynamic RAM circuits, except that the
"latching" mechanism is made for one-time (or limited) operation. The simplest type of ROM is
that which uses tiny "fuses" which can be selectively blown or left alone to represent the two binary
states. Obviously, once one of the little fuses is blown, it cannot be made whole again, so the writing
of such ROM circuits is one-time only. Because it can be written (programmed) once, these circuits
are sometimes referred to as PROMs (Programmable Read-Only Memory).
However, not all writing methods are as permanent as blown fuses. If a transistor latch can
be made which is resettable only with signi¯cant e®ort, a memory device that's something of a
cross between a RAM and a ROM can be built. Such a device is given a rather oxymoronic name:
the EPROM (Erasable Programmable Read-Only Memory). EPROMs come in two basic varieties:
Electrically-erasable (EEPROM) and Ultraviolet-erasable (UV/EPROM). Both types of EPROMs
430 CHAPTER 15. DIGITAL STORAGE (MEMORY)
use capacitive charge MOSFET devices to latch on or o®. UV/EPROMs are "cleared" by long-term
exposure to ultraviolet light. They are easy to identify: they have a transparent glass window which
exposes the silicon chip material to light. Once programmed, you must cover that glass window with
tape to prevent ambient light from degrading the data over time. EPROMs are often programmed
using higher signal voltages than what is used during "read-only" mode.
15.6 Memory with moving parts: "Drives"
The earliest forms of digital data storage involving moving parts was that of the punched paper card.
Joseph Marie Jacquard invented a weaving loom in 1780 which automatically followed weaving
instructions set by carefully placed holes in paper cards. This same technology was adapted to
electronic computers in the 1950's, with the cards being read mechanically (metal-to-metal contact
through the holes), pneumatically (air blown through the holes, the presence of a hole sensed by air
nozzle backpressure), or optically (light shining through the holes).
An improvement over paper cards is the paper tape, still used in some industrial environments
(notably the CNC machine tool industry), where data storage and speed demands are low and
ruggedness is highly valued. Instead of wood-¯ber paper, mylar material is often used, with optical
reading of the tape being the most popular method.
Magnetic tape (very similar to audio or video cassette tape) was the next logical improvement
in storage media. It is still widely used today, as a means to store "backup" data for archiving
and emergency restoration for other, faster methods of data storage. Like paper tape, magnetic
tape is sequential access, rather than random access. In early home computer systems, regular
audio cassette tape was used to store data in modulated form, the binary 1's and 0's represented
by di®erent frequencies (similar to FSK data communication). Access speed was terribly slow (if
you were reading ASCII text from the tape, you could almost keep up with the pace of the letters
appearing on the computer's screen!), but it was cheap and fairly reliable.
Tape su®ered the disadvantage of being sequential access. To address this weak point, magnetic
storage "drives" with disk- or drum-shaped media were built. An electric motor provided constant-
speed motion. A movable read/write coil (also known as a "head") was provided which could be
positioned via servo-motors to various locations on the height of the drum or the radius of the disk,
giving access that is almost random (you might still have to wait for the drum or disk to rotate to
the proper position once the read/write coil has reached the right location).
The disk shape lent itself best to portable media, and thus the °oppy disk was born. Floppy disks
(so-called because the magnetic media is thin and °exible) were originally made in 8-inch diameter
formats. Later, the 5-1/4 inch variety was introduced, which was made practical by advances in
media particle density. All things being equal, a larger disk has more space upon which to write
data. However, storage density can be improved by making the little grains of iron-oxide material
on the disk substrate smaller. Today, the 3-1/2 inch °oppy disk is the preeminent format, with a
capacity of 1.44 Mbytes (2.88 Mbytes on SCSI drives). Other portable drive formats are becoming
popular, with IoMega's 100 Mbyte "ZIP" and 1 Gbyte "JAZ" disks appearing as original equipment
on some personal computers.
Still, °oppy drives have the disadvantage of being exposed to harsh environments, being con-
stantly removed from the drive mechanism which reads, writes, and spins the media. The ¯rst
disks were enclosed units, sealed from all dust and other particulate matter, and were de¯nitely not
portable. Keeping the media in an enclosed environment allowed engineers to avoid dust altogether,
15.6. MEMORY WITH MOVING PARTS: "DRIVES" 431
as well as spurious magnetic ¯elds. This, in turn, allowed for much closer spacing between the head
and the magnetic material, resulting in a much tighter-focused magnetic ¯eld to write data to the
magnetic material.
The following photograph shows a hard disk drive "platter" of approximately 30 Mbytes storage
capacity. A ball-point pen has been set near the bottom of the platter for size reference:
Modern disk drives use multiple platters made of hard material (hence the name, "hard drive")
with multiple read/write heads for every platter. The gap between head and platter is much smaller
than the diameter of a human hair. If the hermetically-sealed environment inside a hard disk drive
is contaminated with outside air, the hard drive will be rendered useless. Dust will lodge between
the heads and the platters, causing damage to the surface of the media.
Here is a hard drive with four platters, although the angle of the shot only allows viewing of the
top platter. This unit is complete with drive motor, read/write heads, and associated electronics.
It has a storage capacity of 340 Mbytes, and is about the same length as the ball-point pen shown
in the previous photograph:
While it is inevitable that non-moving-part technology will replace mechanical drives in the
future, current state-of-the-art electromechanical drives continue to rival "solid-state" nonvolatile
memory devices in storage density, and at a lower cost. In 1998, a 250 Mbyte hard drive was
announced that was approximately the size of a quarter (smaller than the metal platter hub in the
center of the last hard disk photograph)! In any case, storage density and reliability will undoubtedly
continue to improve.
432 CHAPTER 15. DIGITAL STORAGE (MEMORY)
An incentive for digital data storage technology advancement was the advent of digitally encoded
music. A joint venture between Sony and Phillips resulted in the release of the "compact audio disk"
(CD) to the public in the late 1980's. This technology is a read-only type, the media being a thin
¯lm of aluminum foil embedded in a transparent plastic disk. Binary bits are "burned" into the
aluminum as pits by a high-power laser. Data is read by a low-power laser (the beam of which can
be focused more precisely than normal light) re°ecting o® the aluminum to a photocell receiver.
The advantages of CDs over magnetic tape are legion. Being digital, the information is highly
resistant to corruption. Being non-contact in operation, there is no wear incurred through playing.
Being optical, they are immune to magnetic ¯elds (which can easily corrupt data on magnetic tape
or disks). It is possible to purchase CD "burner" drives which contain the high-power laser necessary
to write to a blank disk.
Following on the heels of the music industry, the video entertainment industry has leveraged
the technology of optical storage with the introduction of the Digital Video Disk, or DVD. Using a
similar-sized plastic disk as the music CD, a DVD employs closer spacing of pits to achieve much
greater storage density. This increased density allows feature-length movies to be encoded on DVD
media, complete with trivia information about the movie, director's notes, and so on.
Much e®ort is being directed toward the development of practical read/write optical disks (CD-
W). Success has been found in using chemical substances whose color may be changed through
exposure to bright laser light, then "read" by lower-intensity light. These optical disks are immedi-
ately identi¯ed by their characteristically colored surfaces, as opposed to the silver-colored underside
of a standard CD.
Chapter 16
PRINCIPLES OF DIGITAL
COMPUTING
Contents
16.1 A binary adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
16.2 Look-up tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
16.3 Finite-state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
16.4 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
16.5 Microprocessor programming . . . . . . . . . . . . . . . . . . . . . . . . 445
16.1 A binary adder
Suppose we wanted to build a device that could add two binary bits together. Such a device is
known as a half-adder, and its gate circuit looks like this:
A
B
Cout
S
The § symbol represents the "sum" output of the half-adder, the sum's least signi¯cant bit
(LSB). Cout represents the "carry" output of the half-adder, the sum's most signi¯cant bit (MSB).
If we were to implement this same function in ladder (relay) logic, it would look like this:
433
434 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
L1 L2
A B
A B
A B S
Cout
Either circuit is capable of adding two binary digits together. The mathematical "rules" of
how to add bits together are intrinsic to the hard-wired logic of the circuits. If we wanted to
perform a di®erent arithmetic operation with binary bits, such as multiplication, we would have
to construct another circuit. The above circuit designs will only perform one function: add two
binary bits together. To make them do something else would take re-wiring, and perhaps di®erent
componentry.
In this sense, digital arithmetic circuits aren't much di®erent from analog arithmetic (operational
ampli¯er) circuits: they do exactly what they're wired to do, no more and no less. We are not,
however, restricted to designing digital computer circuits in this manner. It is possible to embed
the mathematical "rules" for any arithmetic operation in the form of digital data rather than in
hard-wired connections between gates. The result is unparalleled °exibility in operation, giving rise
to a whole new kind of digital device: the programmable computer.
While this chapter is by no means exhaustive, it provides what I believe is a unique and interesting
look at the nature of programmable computer devices, starting with two devices often overlooked in
introductory textbooks: look-up table memories and ¯nite-state machines.
16.2 Look-up tables
Having learned about digital memory devices in the last chapter, we know that it is possible to store
binary data within solid-state devices. Those storage "cells" within solid-state memory devices are
easily addressed by driving the "address" lines of the device with the proper binary value(s). Suppose
we had a ROM memory circuit written, or programmed, with certain data, such that the address
lines of the ROM served as inputs and the data lines of the ROM served as outputs, generating the
characteristic response of a particular logic function. Theoretically, we could program this ROM
chip to emulate whatever logic function we wanted without having to alter any wire connections or
gates.
Consider the following example of a 4 x 2 bit ROM memory (a very small memory!) programmed
with the functionality of a half adder:
16.2. LOOK-UP TABLES 435
4 x 2 ROM
A0
A1
D0
D1
A
B
S
Cout
A B Cout S
0 0
0 1
1 0
1 1
0 0
0
0
0
1
1
1
Address Data
If this ROM has been written with the above data (representing a half-adder's truth table),
driving the A and B address inputs will cause the respective memory cells in the ROM chip to be
enabled, thus outputting the corresponding data as the § (Sum) and Cout bits. Unlike the half-adder
circuit built of gates or relays, this device can be set up to perform any logic function at all with two
inputs and two outputs, not just the half-adder function. To change the logic function, all we would
need to do is write a di®erent table of data to another ROM chip. We could even use an EPROM
chip which could be re-written at will, giving the ultimate °exibility in function.
It is vitally important to recognize the signi¯cance of this principle as applied to digital circuitry.
Whereas the half-adder built from gates or relays processes the input bits to arrive at a speci¯c
output, the ROM simply remembers what the outputs should be for any given combination of
inputs. This is not much di®erent from the "times tables" memorized in grade school: rather than
having to calculate the product of 5 times 6 (5 + 5 + 5 + 5 + 5 + 5 = 30), school-children are taught
to remember that 5 x 6 = 30, and then expected to recall this product from memory as needed.
Likewise, rather than the logic function depending on the functional arrangement of hard-wired
gates or relays (hardware), it depends solely on the data written into the memory (software).
Such a simple application, with de¯nite outputs for every input, is called a look-up table, because
the memory device simply "looks up" what the output(s) should to be for any given combination of
inputs states.
This application of a memory device to perform logical functions is signi¯cant for several reasons:
² Software is much easier to change than hardware.
² Software can be archived on various kinds of memory media (disk, tape), thus providing an
easy way to document and manipulate the function in a "virtual" form; hardware can only be
"archived" abstractly in the form of some kind of graphical drawing.
² Software can be copied from one memory device (such as the EPROM chip) to another, allowing
the ability for one device to "learn" its function from another device.
² Software such as the logic function example can be designed to perform functions that would
be extremely di±cult to emulate with discrete logic gates (or relays!).
The usefulness of a look-up table becomes more and more evident with increasing complexity of
function. Suppose we wanted to build a 4-bit adder circuit using a ROM. We'd require a ROM with
8 address lines (two 4-bit numbers to be added together), plus 4 data lines (for the signed output):
436 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
A0
A1 D0
D1
A2
A3
A4
A5
A6
A7
D2
D3
First
4-bit
number
Second
4-bit
number
4-bit
result
256 x 4
ROM
With 256 addressable memory locations in this ROM chip, we would have a fair amount of
programming to do, telling it what binary output to generate for each and every combination of
binary inputs. We would also run the risk of making a mistake in our programming and have it
output an incorrect sum, if we weren't careful. However, the °exibility of being able to con¯gure
this function (or any function) through software alone generally outweighs that costs.
Consider some of the advanced functions we could implement with the above "adder." We know
that when we add two sets of numbers in 2's complement signed notation, we risk having the answer
over°ow. For instance, if we try to add 0111 (decimal 7) to 0110 (decimal 6) with only a 4-bit
number ¯eld, the answer we'll get is 1001 (decimal -7) instead of the correct value, 13 (7 + 6), which
cannot be expressed using 4 signed bits. If we wanted to, we could avoid the strange answers given in
over°ow conditions by programming this look-up table circuit to output something else in conditions
where we know over°ow will occur (that is, in any case where the real sum would exceed +7 or -8).
One alternative might be to program the ROM to output the quantity 0111 (the maximum positive
value that can be represented with 4 signed bits), or any other value that we determined to be more
appropriate for the application than the typical over°owed "error" value that a regular adder circuit
would output. It's all up to the programmer to decide what he or she wants this circuit to do,
because we are no longer limited by the constraints of logic gate functions.
The possibilities don't stop at customized logic functions, either. By adding more address lines
to the 256 x 4 ROM chip, we can expand the look-up table to include multiple functions:
16.2. LOOK-UP TABLES 437
A0
A1 D0
D1
A2
A3
A4
A5
A6
A7
D2
D3
First
4-bit
number
Second
4-bit
number
4-bit
result
ROM
Function
control
A8
A9
1024 x 4
With two more address lines, the ROM chip will have 4 times as many addresses as before (1024
instead of 256). This ROM could be programmed so that when A8 and A9 were both low, the output
data represented the sum of the two 4-bit binary numbers input on address lines A0 through A7,
just as we had with the previous 256 x 4 ROM circuit. For the addresses A8=1 and A9=0, it could
be programmed to output the di®erence (subtraction) between the ¯rst 4-bit binary number (A0
through A3) and the second binary number (A4 through A7). For the addresses A8=0 and A9=1, we
could program the ROM to output the di®erence (subtraction) of the two numbers in reverse order
(second - ¯rst rather than ¯rst - second), and ¯nally, for the addresses A8=1 and A9=1, the ROM
could be programmed to compare the two inputs and output an indication of equality or inequality.
What we will have then is a device that can perform four di®erent arithmetical operations on 4-bit
binary numbers, all by "looking up" the answers programmed into it.
If we had used a ROM chip with more than two additional address lines, we could program
it with a wider variety of functions to perform on the two 4-bit inputs. There are a number of
operations peculiar to binary data (such as parity check or Exclusive-ORing of bits) that we might
¯nd useful to have programmed in such a look-up table.
Devices such as this, which can perform a variety of arithmetical tasks as dictated by a binary
input code, are known as Arithmetic Logic Units (ALUs), and they comprise one of the essential
components of computer technology. Although modern ALUs are more often constructed from very
complex combinational logic (gate) circuits for reasons of speed, it should be comforting to know
that the exact same functionality may be duplicated with a "dumb" ROM chip programmed with
the appropriate look-up table(s). In fact, this exact approach was used by IBM engineers in 1959
with the development of the IBM 1401 and 1620 computers, which used look-up tables to perform
addition, rather than binary adder circuitry. The machine was fondly known as the "CADET,"
which stood for "Can't Add, Doesn't Even Try."
A very common application for look-up table ROMs is in control systems where a custom math-
ematical function needs to be represented. Such an application is found in computer-controlled fuel
injection systems for automobile engines, where the proper air/fuel mixture ratio for e±cient and
438 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
clean operation changes with several environmental and operational variables. Tests performed on
engines in research laboratories determine what these ideal ratios are for varying conditions of en-
gine load, ambient air temperature, and barometric air pressure. The variables are measured with
sensor transducers, their analog outputs converted to digital signals with A/D circuitry, and those
parallel digital signals used as address inputs to a high-capacity ROM chip programmed to output
the optimum digital value for air/fuel ratio for any of these given conditions.
Sometimes, ROMs are used to provide one-dimensional look-up table functions, for "correcting"
digitized signal values so that they more accurately represent their real-world signi¯cance. An exam-
ple of such a device is a thermocouple transmitter, which measures the millivoltage signal generated
by a junction of dissimilar metals and outputs a signal which is supposed to directly correspond
to that junction temperature. Unfortunately, thermocouple junctions do not have perfectly linear
temperature/voltage responses, and so the raw voltage signal is not perfectly proportional to tem-
perature. By digitizing the voltage signal (A/D conversion) and sending that digital value to the
address of a ROM programmed with the necessary correction values, the ROM's programming could
eliminate some of the nonlinearity of the thermocouple's temperature-to-millivoltage relationship,
so that the ¯nal output of the device would be more accurate. The popular instrumentation term
for such a look-up table is a digital characterizer.
A/D
converter
ROM
converter
D/A 4-20 mA
analog
signal
Another application for look-up tables is in special code translation. A 128 x 8 ROM, for instance,
could be used to translate 7-bit ASCII code to 8-bit EBCDIC code:
A0
A1
D0
D1
A2
A3
A4
A5
A6
D2
D3
ROM
D4
D5
D6
D7
128 x 8
ASCII
in EBCDIC
out
Again, all that is required is for the ROM chip to be properly programmed with the necessary
data so that each valid ASCII input will produce a corresponding EBCDIC output code.
16.3. FINITE-STATE MACHINES 439
16.3 Finite-state machines
Feedback is a fascinating engineering principle. It can turn a rather simple device or process into
something substantially more complex. We've seen the e®ects of feedback intentionally integrated
into circuit designs with some rather astounding e®ects:
² Comparator + negative feedback |||{> controllable-gain ampli¯er
² Comparator + positive feedback |||{> comparator with hysteresis
² Combinational logic + positive feedback {> multivibrator
In the ¯eld of process instrumentation, feedback is used to transform a simple measurement
system into something capable of control:
² Measurement system + negative feedback |> closed-loop control system
Feedback, both positive and negative, has the tendency to add whole new dynamics to the
operation of a device or system. Sometimes, these new dynamics ¯nd useful application, while other
times they are merely interesting. With look-up tables programmed into memory devices, feedback
from the data outputs back to the address inputs creates a whole new type of device: the Finite
State Machine, or FSM:
A0
A1
D0
D1
A2
A3
D2
D3
ROM
16 x 4
A crude Finite State Machine
Feedback
D0
D1
D2
D3
The above circuit illustrates the basic idea: the data stored at each address becomes the next
storage location that the ROM gets addressed to. The result is a speci¯c sequence of binary numbers
(following the sequence programmed into the ROM) at the output, over time. To avoid signal timing
problems, though, we need to connect the data outputs back to the address inputs through a 4-bit
D-type °ip-°op, so that the sequence takes place step by step to the beat of a controlled clock pulse:
440 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
A0
A1
D0
D1
A2
A3
D2
D3
ROM
16 x 4
Feedback
D0
D1
D2
D3
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SRG
Clock
An improved Finite State Machine
An analogy for the workings of such a device might be an array of post-o±ce boxes, each one
with an identifying number on the door (the address), and each one containing a piece of paper with
the address of another P.O. box written on it (the data). A person, opening the ¯rst P.O. box, would
¯nd in it the address of the next P.O. box to open. By storing a particular pattern of addresses
in the P.O. boxes, we can dictate the sequence in which each box gets opened, and therefore the
sequence of which paper gets read.
Having 16 addressable memory locations in the ROM, this Finite State Machine would have 16
di®erent stable "states" in which it could latch. In each of those states, the identity of the next state
would be programmed in to the ROM, awaiting the signal of the next clock pulse to be fed back to
the ROM as an address. One useful application of such an FSM would be to generate an arbitrary
count sequence, such as Gray Code:
Address -----> Data Gray Code count sequence:
0000 -------> 0001 0 0000
0001 -------> 0011 1 0001
0010 -------> 0110 2 0011
0011 -------> 0010 3 0010
0100 -------> 1100 4 0110
0101 -------> 0100 5 0111
0110 -------> 0111 6 0101
0111 -------> 0101 7 0100
1000 -------> 0000 8 1100
1001 -------> 1000 9 1101
1010 -------> 1011 10 1111
1011 -------> 1001 11 1110
1100 -------> 1101 12 1010
1101 -------> 1111 13 1011
16.3. FINITE-STATE MACHINES 441
1110 -------> 1010 14 1001
1111 -------> 1110 15 1000
Try to follow the Gray Code count sequence as the FSM would do it: starting at 0000, follow
the data stored at that address (0001) to the next address, and so on (0011), and so on (0010), and
so on (0110), etc. The result, for the program table shown, is that the sequence of addressing jumps
around from address to address in what looks like a haphazard fashion, but when you check each
address that is accessed, you will ¯nd that it follows the correct order for 4-bit Gray code. When
the FSM arrives at its last programmed state (address 1000), the data stored there is 0000, which
starts the whole sequence over again at address 0000 in step with the next clock pulse.
We could expand on the capabilities of the above circuit by using a ROM with more address
lines, and adding more programming data:
A0
A1
D0
D1
A2
A3
D2
D3
ROM
Feedback
D0
D1
D2
D3
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SRG
Clock
D4 Q4 A4
"function control"
32 x 4
Now, just like the look-up table adder circuit that we turned into an Arithmetic Logic Unit (+,
-, x, / functions) by utilizing more address lines as "function control" inputs, this FSM counter can
be used to generate more than one count sequence, a di®erent sequence programmed for the four
feedback bits (A0 through A3) for each of the two function control line input combinations (A4 =
0 or 1).
Address -----> Data Address -----> Data
00000 -------> 0001 10000 -------> 0001
00001 -------> 0010 10001 -------> 0011
00010 -------> 0011 10010 -------> 0110
00011 -------> 0100 10011 -------> 0010
00100 -------> 0101 10100 -------> 1100
00101 -------> 0110 10101 -------> 0100
00110 -------> 0111 10110 -------> 0111
442 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
00111 -------> 1000 10111 -------> 0101
01000 -------> 1001 11000 -------> 0000
01001 -------> 1010 11001 -------> 1000
01010 -------> 1011 11010 -------> 1011
01011 -------> 1100 11011 -------> 1001
01100 -------> 1101 11100 -------> 1101
01101 -------> 1110 11101 -------> 1111
01110 -------> 1111 11110 -------> 1010
01111 -------> 0000 11111 -------> 1110
If A4 is 0, the FSM counts in binary; if A4 is 1, the FSM counts in Gray Code. In either case, the
counting sequence is arbitrary: determined by the whim of the programmer. For that matter, the
counting sequence doesn't even have to have 16 steps, as the programmer may decide to have the
sequence recycle to 0000 at any one of the steps at all. It is a completely °exible counting device,
the behavior strictly determined by the software (programming) in the ROM.
We can expand on the capabilities of the FSM even more by utilizing a ROM chip with additional
address input and data output lines. Take the following circuit, for example:
A0
A1
D0
D1
A2
A3
D2
D3
ROM
Feedback
D0
D1
D2
D3
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SRG
Clock
D4 Q4 A4 D4
D5
D6
D7
A5
A6
A7
D5
D6
D7
Q5
Q6
Q7
Inputs Outputs
256 x 8
Here, the D0 through D3 data outputs are used exclusively for feedback to the A0 through A3
address lines. Date output lines D4 through D7 can be programmed to output something other than
the FSM's "state" value. Being that four data output bits are being fed back to four address bits,
this is still a 16-state device. However, having the output data come from other data output lines
gives the programmer more freedom to con¯gure functions than before. In other words, this device
16.4. MICROPROCESSORS 443
can do far more than just count! The programmed output of this FSM is dependent not only upon
the state of the feedback address lines (A0 through A3), but also the states of the input lines (A4
through A7). The D-type °ip/°op's clock signal input does not have to come from a pulse generator,
either. To make things more interesting, the °ip/°op could be wired up to clock on some external
event, so that the FSM goes to the next state only when an input signal tells it to.
Now we have a device that better ful¯lls the meaning of the word "programmable." The data
written to the ROM is a program in the truest sense: the outputs follow a pre-established order based
on the inputs to the device and which "step" the device is on in its sequence. This is very close to the
operating design of the Turing Machine, a theoretical computing device invented by Alan Turing,
mathematically proven to be able to solve any known arithmetic problem, given enough memory
capacity.
16.4 Microprocessors
Early computer science pioneers such as Alan Turing and John Von Neumann postulated that for
a computing device to be really useful, it not only had to be able to generate speci¯c outputs as
dictated by programmed instructions, but it also had to be able to write data to memory, and be
able to act on that data later. Both the program steps and the processed data were to reside in
a common memory "pool," thus giving way to the label of the stored-program computer. Turing's
theoretical machine utilized a sequential-access tape, which would store data for a control circuit to
read, the control circuit re-writing data to the tape and/or moving the tape to a new position to
read more data. Modern computers use random-access memory devices instead of sequential-access
tapes to accomplish essentially the same thing, except with greater capability.
A helpful illustration is that of early automatic machine tool control technology. Called open-
loop, or sometimes just NC (numerical control), these control systems would direct the motion of a
machine tool such as a lathe or a mill by following instructions programmed as holes in paper tape.
The tape would be run one direction through a "read" mechanism, and the machine would blindly
follow the instructions on the tape without regard to any other conditions. While these devices
eliminated the burden of having to have a human machinist direct every motion of the machine tool,
it was limited in usefulness. Because the machine was blind to the real world, only following the
instructions written on the tape, it could not compensate for changing conditions such as expansion
of the metal or wear of the mechanisms. Also, the tape programmer had to be acutely aware of the
sequence of previous instructions in the machine's program to avoid troublesome circumstances (such
as telling the machine tool to move the drill bit laterally while it is still inserted into a hole in the
work), since the device had no memory other than the tape itself, which was read-only. Upgrading
from a simple tape reader to a Finite State control design gave the device a sort of memory that
could be used to keep track of what it had already done (through feedback of some of the data bits
to the address bits), so at least the programmer could decide to have the circuit remember "states"
that the machine tool could be in (such as "coolant on," or tool position). However, there was still
room for improvement.
The ultimate approach is to have the program give instructions which would include the writing
of new data to a read/write (RAM) memory, which the program could easily recall and process.
This way, the control system could record what it had done, and any sensor-detectable process
changes, much in the same way that a human machinist might jot down notes or measurements on a
scratch-pad for future reference in his or her work. This is what is referred to as CNC, or Closed-loop
444 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
Numerical Control.
Engineers and computer scientists looked forward to the possibility of building digital devices
that could modify their own programming, much the same as the human brain adapts the strength
of inter-neural connections depending on environmental experiences (that is why memory retention
improves with repeated study, and behavior is modi¯ed through consequential feedback). Only if
the computer's program were stored in the same writable memory "pool" as the data would this
be practical. It is interesting to note that the notion of a self-modifying program is still considered
to be on the cutting edge of computer science. Most computer programming relies on rather ¯xed
sequences of instructions, with a separate ¯eld of data being the only information that gets altered.
To facilitate the stored-program approach, we require a device that is much more complex than
the simple FSM, although many of the same principles apply. First, we need read/write memory
that can be easily accessed: this is easy enough to do. Static or dynamic RAM chips do the job well,
and are inexpensive. Secondly, we need some form of logic to process the data stored in memory.
Because standard and Boolean arithmetic functions are so useful, we can use an Arithmetic Logic
Unit (ALU) such as the look-up table ROM example explored earlier. Finally, we need a device
that controls how and where data °ows between the memory, the ALU, and the outside world. This
so-called Control Unit is the most mysterious piece of the puzzle yet, being comprised of tri-state
bu®ers (to direct data to and from buses) and decoding logic which interprets certain binary codes
as instructions to carry out. Sample instructions might be something like: "add the number stored
at memory address 0010 with the number stored at memory address 1101," or, "determine the parity
of the data in memory address 0111." The choice of which binary codes represent which instructions
for the Control Unit to decode is largely arbitrary, just as the choice of which binary codes to use
in representing the letters of the alphabet in the ASCII standard was largely arbitrary. ASCII,
however, is now an internationally recognized standard, whereas control unit instruction codes are
almost always manufacturer-speci¯c.
Putting these components together (read/write memory, ALU, and control unit) results in a
digital device that is typically called a processor. If minimal memory is used, and all the necessary
components are contained on a single integrated circuit, it is called a microprocessor. When combined
with the necessary bus-control support circuitry, it is known as a Central Processing Unit, or CPU.
CPU operation is summed up in the so-called fetch/execute cycle. Fetch means to read an
instruction from memory for the Control Unit to decode. A small binary counter in the CPU (known
as the program counter or instruction pointer) holds the address value where the next instruction
is stored in main memory. The Control Unit sends this binary address value to the main memory's
address lines, and the memory's data output is read by the Control Unit to send to another holding
register. If the fetched instruction requires reading more data from memory (for example, in adding
two numbers together, we have to read both the numbers that are to be added from main memory or
from some other source), the Control Unit appropriately addresses the location of the requested data
and directs the data output to ALU registers. Next, the Control Unit would execute the instruction
by signaling the ALU to do whatever was requested with the two numbers, and direct the result to
another register called the accumulator. The instruction has now been "fetched" and "executed,"
so the Control Unit now increments the program counter to step the next instruction, and the cycle
repeats itself.
Microprocessor (CPU)
--------------------------------------
j ** Program counter ** j
16.5. MICROPROCESSOR PROGRAMMING 445
j (increments address value sent to j
j external memory chip(s) to fetch j==========> Address bus
j the next instruction) j (to RAM memory)
--------------------------------------
j ** Control Unit ** j<=========> Control Bus
j (decodes instructions read from j (to all devices sharing
j program in memory, enables flow j address and/or data busses;
j of data to and from ALU, internal j arbitrates all bus communi-
j registers, and external devices) j cations)
--------------------------------------
j ** Arithmetic Logic Unit (ALU) ** j
j (performs all mathematical j
j calculations and Boolean j
j functions) j
--------------------------------------
j ** Registers ** j
j (small read/write memories for j<=========> Data Bus
j holding instruction codes, j (from RAM memory and other
j error codes, ALU data, etc; j external devices)
j includes the "accumulator") j
--------------------------------------
As one might guess, carrying out even simple instructions is a tedious process. Several steps
are necessary for the Control Unit to complete the simplest of mathematical procedures. This
is especially true for arithmetic procedures such as exponents, which involve repeated executions
("iterations") of simpler functions. Just imagine the sheer quantity of steps necessary within the
CPU to update the bits of information for the graphic display on a °ight simulator game! The only
thing which makes such a tedious process practical is the fact that microprocessor circuits are able
to repeat the fetch/execute cycle with great speed.
In some microprocessor designs, there are minimal programs stored within a special ROM mem-
ory internal to the device (called microcode) which handle all the sub-steps necessary to carry out
more complex math operations. This way, only a single instruction has to be read from the program
RAM to do the task, and the programmer doesn't have to deal with trying to tell the microprocessor
how to do every minute step. In essence, it's a processor inside of a processor; a program running
inside of a program.
16.5 Microprocessor programming
The "vocabulary" of instructions which any particular microprocessor chip possesses is speci¯c to
that model of chip. An Intel 80386, for example, uses a completely di®erent set of binary codes
than a Motorola 68020, for designating equivalent functions. Unfortunately, there are no standards
in place for microprocessor instructions. This makes programming at the very lowest level very
confusing and specialized.
When a human programmer develops a set of instructions to directly tell a microprocessor how to
do something (like automatically control the fuel injection rate to an engine), they're programming
446 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
in the CPU's own "language." This language, which consists of the very same binary codes which
the Control Unit inside the CPU chip decodes to perform tasks, is often referred to as machine
language. While machine language software can be "worded" in binary notation, it is often written
in hexadecimal form, because it is easier for human beings to work with. For example, I'll present
just a few of the common instruction codes for the Intel 8080 micro-processor chip:
Hexadecimal Binary Instruction description
----------- -------- -----------------------------------------
j 7B 01111011 Move contents of register A to register E
j
j 87 10000111 Add contents of register A to register D
j
j 1C 00011100 Increment the contents of register E by 1
j
j D3 11010011 Output byte of data to data bus
Even with hexadecimal notation, these instructions can be easily confused and forgotten. For
this purpose, another aid for programmers exists called assembly language. With assembly language,
two to four letter mnemonic words are used in place of the actual hex or binary code for describing
program steps. For example, the instruction 7B for the Intel 8080 would be "MOV A,E" in assembly
language. The mnemonics, of course, are useless to the microprocessor, which can only understand
binary codes, but it is an expedient way for programmers to manage the writing of their programs
on paper or text editor (word processor). There are even programs written for computers called
assemblers which understand these mnemonics, translating them to the appropriate binary codes
for a speci¯ed target microprocessor, so that the programmer can write a program in the computer's
native language without ever having to deal with strange hex or tedious binary code notation.
Once a program is developed by a person, it must be written into memory before a microprocessor
can execute it. If the program is to be stored in ROM (which some are), this can be done with a
special machine called a ROM programmer, or (if you're masochistic), by plugging the ROM chip into
a breadboard, powering it up with the appropriate voltages, and writing data by making the right
wire connections to the address and data lines, one at a time, for each instruction. If the program
is to be stored in volatile memory, such as the operating computer's RAM memory, there may be a
way to type it in by hand through that computer's keyboard (some computers have a mini-program
stored in ROM which tells the microprocessor how to accept keystrokes from a keyboard and store
them as commands in RAM), even if it is too dumb to do anything else. Many "hobby" computer
kits work like this. If the computer to be programmed is a fully-functional personal computer with
an operating system, disk drives, and the whole works, you can simply command the assembler
to store your ¯nished program onto a disk for later retrieval. To "run" your program, you would
simply type your program's ¯lename at the prompt, press the Enter key, and the microprocessor's
Program Counter register would be set to point to the location ("address") on the disk where the
¯rst instruction is stored, and your program would run from there.
Although programming in machine language or assembly language makes for fast and highly
e±cient programs, it takes a lot of time and skill to do so for anything but the simplest tasks,
because each machine language instruction is so crude. The answer to this is to develop ways for
programmers to write in "high level" languages, which can more e±ciently express human thought.
16.5. MICROPROCESSOR PROGRAMMING 447
Instead of typing in dozens of cryptic assembly language codes, a programmer writing in a high-level
language would be able to write something like this . . .
Print "Hello, world!"
. . . and expect the computer to print "Hello, world!" with no further instruction on how to do
so. This is a great idea, but how does a microprocessor understand such "human" thinking when
its vocabulary is so limited?
The answer comes in two di®erent forms: interpretation, or compilation. Just like two people
speaking di®erent languages, there has to be some way to transcend the language barrier in order
for them to converse. A translator is needed to translate each person's words to the other person's
language, one way at a time. For the microprocessor, this means another program, written by
another programmer in machine language, which recognizes the ASCII character patterns of high-
level commands such as Print (P-r-i-n-t) and can translate them into the necessary bite-size steps that
the microprocessor can directly understand. If this translation is done during program execution, just
like a translator intervening between two people in a live conversation, it is called "interpretation."
On the other hand, if the entire program is translated to machine language in one fell swoop, like a
translator recording a monologue on paper and then translating all the words at one sitting into a
written document in the other language, the process is called "compilation."
Interpretation is simple, but makes for a slow-running program because the microprocessor has
to continually translate the program between steps, and that takes time. Compilation takes time
initially to translate the whole program into machine code, but the resulting machine code needs no
translation after that and runs faster as a consequence. Programming languages such as BASIC and
FORTH are interpreted. Languages such as C, C++, FORTRAN, and PASCAL are compiled. Com-
piled languages are generally considered to be the languages of choice for professional programmers,
because of the e±ciency of the ¯nal product.
Naturally, because machine language vocabularies vary widely from microprocessor to micropro-
cessor, and since high-level languages are designed to be as universal as possible, the interpreting
and compiling programs necessary for language translation must be microprocessor-speci¯c. Devel-
opment of these interpreters and compilers is a most impressive feat: the people who make these
programs most de¯nitely earn their keep, especially when you consider the work they must do to
keep their software product current with the rapidly-changing microprocessor models appearing on
the market!
To mitigate this di±culty, the trend-setting manufacturers of microprocessor chips (most notably,
Intel and Motorola) try to design their new products to be backwardly compatible with their older
products. For example, the entire instruction set for the Intel 80386 chip is contained within the
latest Pentium IV chips, although the Pentium chips have additional instructions that the 80386
chips lack. What this means is that machine-language programs (compilers, too) written for 80386
computers will run on the latest and greatest Intel Pentium IV CPU, but machine-language programs
written speci¯cally to take advantage of the Pentium's larger instruction set will not run on an 80386,
because the older CPU simply doesn't have some of those instructions in its vocabulary: the Control
Unit inside the 80386 cannot decode them.
Building on this theme, most compilers have settings that allow the programmer to select which
CPU type he or she wants to compile machine-language code for. If they select the 80386 setting, the
compiler will perform the translation using only instructions known to the 80386 chip; if they select
the Pentium setting, the compiler is free to make use of all instructions known to Pentiums. This
448 CHAPTER 16. PRINCIPLES OF DIGITAL COMPUTING
is analogous to telling a translator what minimum reading level their audience will be: a document
translated for a child will be understandable to an adult, but a document translated for an adult
may very well be gibberish to a child.
Appendix A-1
ABOUT THIS BOOK
A-1.1 Purpose
They say that necessity is the mother of invention. At least in the case of this book, that adage
is true. As an industrial electronics instructor, I was forced to use a sub-standard textbook during
my ¯rst year of teaching. My students were daily frustrated with the many typographical errors
and obscure explanations in this book, having spent much time at home struggling to comprehend
the material within. Worse yet were the many incorrect answers in the back of the book to selected
problems. Adding insult to injury was the $100+ price.
Contacting the publisher proved to be an exercise in futility. Even though the particular text I
was using had been in print and in popular use for a couple of years, they claimed my complaint
was the ¯rst they'd ever heard. My request to review the draft for the next edition of their book
was met with disinterest on their part, and I resolved to ¯nd an alternative text.
Finding a suitable alternative was more di±cult than I had imagined. Sure, there were plenty of
texts in print, but the really good books seemed a bit too heavy on the math and the less intimidating
books omitted a lot of information I felt was important. Some of the best books were out of print,
and those that were still being printed were quite expensive.
It was out of frustration that I compiled Lessons in Electric Circuits from notes and ideas I had
been collecting for years. My primary goal was to put readable, high-quality information into the
hands of my students, but a secondary goal was to make the book as a®ordable as possible. Over the
years, I had experienced the bene¯t of receiving free instruction and encouragement in my pursuit
of learning electronics from many people, including several teachers of mine in elementary and high
school. Their sel°ess assistance played a key role in my own studies, paving the way for a rewarding
career and fascinating hobby. If only I could extend the gift of their help by giving to other people
what they gave to me . . .
So, I decided to make the book freely available. More than that, I decided to make it "open,"
following the same development model used in the making of free software (most notably the various
UNIX utilities released by the Free Software Foundation, and the Linux operating system, whose
fame is growing even as I write). The goal was to copyright the text { so as to protect my authorship
449
450 APPENDIX A-1. ABOUT THIS BOOK
{ but expressly allow anyone to distribute and/or modify the text to suit their own needs with a
minimum of legal encumbrance. This willful and formal revoking of standard distribution limitations
under copyright is whimsically termed copyleft. Anyone can "copyleft" their creative work simply
by appending a notice to that e®ect on their work, but several Licenses already exist, covering the
¯ne legal points in great detail.
The ¯rst such License I applied to my work was the GPL { General Public License { of the
Free Software Foundation (GNU). The GPL, however, is intended to copyleft works of computer
software, and although its introductory language is broad enough to cover works of text, its wording
is not as clear as it could be for that application. When other, less speci¯c copyleft Licenses began
appearing within the free software community, I chose one of them (the Design Science License, or
DSL) as the o±cial notice for my project.
In "copylefting" this text, I guaranteed that no instructor would be limited by a text insu±cient
for their needs, as I had been with error-ridden textbooks from major publishers. I'm sure this book
in its initial form will not satisfy everyone, but anyone has the freedom to change it, leveraging my
e®orts to suit variant and individual requirements. For the beginning student of electronics, learn
what you can from this book, editing it as you feel necessary if you come across a useful piece of
information. Then, if you pass it on to someone else, you will be giving them something better than
what you received. For the instructor or electronics professional, feel free to use this as a reference
manual, adding or editing to your heart's content. The only "catch" is this: if you plan to distribute
your modi¯ed version of this text, you must give credit where credit is due (to me, the original
author, and anyone else whose modi¯cations are contained in your version), and you must ensure
that whoever you give the text to is aware of their freedom to similarly share and edit the text. The
next chapter covers this process in more detail.
It must be mentioned that although I strive to maintain technical accuracy in all of this book's
content, the subject matter is broad and harbors many potential dangers. Electricity maims and
kills without provocation, and deserves the utmost respect. I strongly encourage experimentation
on the part of the reader, but only with circuits powered by small batteries where there is no risk of
electric shock, ¯re, explosion, etc. High-power electric circuits should be left to the care of trained
professionals! The Design Science License clearly states that neither I nor any contributors to this
book bear any liability for what is done with its contents.
A-1.2 The use of SPICE
One of the best ways to learn how things work is to follow the inductive approach: to observe
speci¯c instances of things working and derive general conclusions from those observations. In
science education, labwork is the traditionally accepted venue for this type of learning, although
in many cases labs are designed by educators to reinforce principles previously learned through
lecture or textbook reading, rather than to allow the student to learn on their own through a truly
exploratory process.
Having taught myself most of the electronics that I know, I appreciate the sense of frustration
students may have in teaching themselves from books. Although electronic components are typically
inexpensive, not everyone has the means or opportunity to set up a laboratory in their own homes,
and when things go wrong there's no one to ask for help. Most textbooks seem to approach the task
of education from a deductive perspective: tell the student how things are supposed to work, then
apply those principles to speci¯c instances that the student may or may not be able to explore by
A-1.3. ACKNOWLEDGEMENTS 451
themselves. The inductive approach, as useful as it is, is hard to ¯nd in the pages of a book.
However, textbooks don't have to be this way. I discovered this when I started to learn a
computer program called SPICE. It is a text-based piece of software intended to model circuits and
provide analyses of voltage, current, frequency, etc. Although nothing is quite as good as building
real circuits to gain knowledge in electronics, computer simulation is an excellent alternative. In
learning how to use this powerful tool, I made a discovery: SPICE could be used within a textbook
to present circuit simulations to allow students to "observe" the phenomena for themselves. This
way, the readers could learn the concepts inductively (by interpreting SPICE's output) as well as
deductively (by interpreting my explanations). Furthermore, in seeing SPICE used over and over
again, they should be able to understand how to use it themselves, providing a perfectly safe means
of experimentation on their own computers with circuit simulations of their own design.
Another advantage to including computer analyses in a textbook is the empirical veri¯cation
it adds to the concepts presented. Without demonstrations, the reader is left to take the author's
statements on faith, trusting that what has been written is indeed accurate. The problem with
faith, of course, is that it is only as good as the authority in which it is placed and the accuracy
of interpretation through which it is understood. Authors, like all human beings, are liable to err
and/or communicate poorly. With demonstrations, however, the reader can immediately see for
themselves that what the author describes is indeed true. Demonstrations also serve to clarify the
meaning of the text with concrete examples.
SPICE is introduced early in volume I (DC) of this book series, and hopefully in a gentle enough
way that it doesn't create confusion. For those wishing to learn more, a chapter in the Reference
volume (volume V) contains an overview of SPICE with many example circuits. There may be more
°ashy (graphic) circuit simulation programs in existence, but SPICE is free, a virtue complementing
the charitable philosophy of this book very nicely.
A-1.3 Acknowledgements
First, I wish to thank my wife, whose patience during those many and long evenings (and weekends!)
of typing has been extraordinary.
I also wish to thank those whose open-source software development e®orts have made this en-
deavor all the more a®ordable and pleasurable. The following is a list of various free computer
software used to make this book, and the respective programmers:
² GNU/Linux Operating System { Linus Torvalds, Richard Stallman, and a host of others too
numerous to mention.
² Vim text editor { Bram Moolenaar and others.
² Xcircuit drafting program { Tim Edwards.
² SPICE circuit simulation program { too many contributors to mention.
² TEX text processing system { Donald Knuth and others.
² Texinfo document formatting system { Free Software Foundation.
² LATEX document formatting system { Leslie Lamport and others.
452 APPENDIX A-1. ABOUT THIS BOOK
² Gimp image manipulation program { too many contributors to mention.
Appreciation is also extended to Robert L. Boylestad, whose ¯rst edition of Introductory Circuit
Analysis taught me more about electric circuits than any other book. Other important texts in
my electronics studies include the 1939 edition of The "Radio" Handbook, Bernard Grob's second
edition of Introduction to Electronics I, and Forrest Mims' original Engineer's Notebook.
Thanks to the sta® of the Bellingham Antique Radio Museum, who were generous enough to
let me terrorize their establishment with my camera and °ash unit. Thanks as well to David
Randolph of the Arlington Water Treatment facility in Arlington, Washington, for allowing me to
take photographs of the equipment during a technical tour.
I wish to speci¯cally thank Je®rey Elkner and all those at Yorktown High School for being willing
to host my book as part of their Open Book Project, and to make the ¯rst e®ort in contributing to its
form and content. Thanks also to David Sweet (website: (http://www.andamooka.org)) and Ben
Crowell (website: (http://www.lightandmatter.com)) for providing encouragement, constructive
criticism, and a wider audience for the online version of this book.
Thanks to Michael Stutz for drafting his Design Science License, and to Richard Stallman for
pioneering the concept of copyleft.
Last but certainly not least, many thanks to my parents and those teachers of mine who saw in
me a desire to learn about electricity, and who kindled that °ame into a passion for discovery and
intellectual adventure. I honor you by helping others as you have helped me.
Tony Kuphaldt, July 2001
"A candle loses nothing of its light when lighting another"
Kahlil Gibran
Appendix A-2
CONTRIBUTOR LIST
A-2.1 How to contribute to this book
As a copylefted work, this book is open to revision and expansion by any interested parties. The
only "catch" is that credit must be given where credit is due. This is a copyrighted work: it is not
in the public domain!
If you wish to cite portions of this book in a work of your own, you must follow the same
guidelines as for any other copyrighted work. Here is a sample from the Design Science License:
The Work is copyright the Author. All rights to the Work are reserved
by the Author, except as specifically described below. This License
describes the terms and conditions under which the Author permits you
to copy, distribute and modify copies of the Work.
In addition, you may refer to the Work, talk about it, and (as
dictated by "fair use") quote from it, just as you would any
copyrighted material under copyright law.
Your right to operate, perform, read or otherwise interpret and/or
execute the Work is unrestricted; however, you do so at your own risk,
because the Work comes WITHOUT ANY WARRANTY -- see Section 7 ("NO
WARRANTY") below.
If you wish to modify this book in any way, you must document the nature of those modi¯cations
in the "Credits" section along with your name, and ideally, information concerning how you may be
contacted. Again, the Design Science License:
Permission is granted to modify or sample from a copy of the Work,
producing a derivative work, and to distribute the derivative work
under the terms described in the section for distribution above,
453
454 APPENDIX A-2. CONTRIBUTOR LIST
provided that the following terms are met:
(a) The new, derivative work is published under the terms of this
License.
(b) The derivative work is given a new name, so that its name or
title can not be confused with the Work, or with a version of
the Work, in any way.
(c) Appropriate authorship credit is given: for the differences
between the Work and the new derivative work, authorship is
attributed to you, while the material sampled or used from
the Work remains attributed to the original Author; appropriate
notice must be included with the new work indicating the nature
and the dates of any modifications of the Work made by you.
Given the complexities and security issues surrounding the maintenance of ¯les comprising this
book, it is recommended that you submit any revisions or expansions to the original author (Tony R.
Kuphaldt). You are, of course, welcome to modify this book directly by editing your own personal
copy, but we would all stand to bene¯t from your contributions if your ideas were incorporated into
the online \master copy" where all the world can see it.
A-2.2 Credits
All entries arranged in alphabetical order of surname. Major contributions are listed by individual
name with some detail on the nature of the contribution(s), date, contact info, etc. Minor contri-
butions (typo corrections, etc.) are listed by name only for reasons of brevity. Please understand
that when I classify a contribution as \minor," it is in no way inferior to the e®ort or value of a
\major" contribution, just smaller in the sense of less text changed. Any and all contributions are
gratefully accepted. I am indebted to all those who have given freely of their own knowledge, time,
and resources to make this a better book!
A-2.2.1 Tony R. Kuphaldt
² Date(s) of contribution(s): 1996 to present
² Nature of contribution: Original author.
² Contact at: liec0@lycos.com
A-2.2.2 Dennis Crunkilton
² Date(s) of contribution(s): July 2004 to present
² Nature of contribution: Karnaugh mapping chapter; 04/2004.
A-2.2. CREDITS 455
² Nature of contribution: Mini table of contents, all chapters except appedicies; html, latex,
ps, pdf; See Devel/tutorial.html; 01/2006.
² Contact at: dcrunkilton(at)att(dot)net
A-2.2.3 Your name here
² Date(s) of contribution(s): Month and year of contribution
² Nature of contribution: Insert text here, describing how you contributed to the book.
² Contact at: my email@provider.net
A-2.2.4 Typo corrections and other \minor" contributions
² line-allaboutcircuits.com (June 2005) Typographical error correction in Volumes 1,2,3,5,
various chapters ,(:s/visa-versa/vice versa/).
² Dennis Crunkilton (October 2005) Typographical capitlization correction to sectiontitles,
chapter 9.
² Je® DeFreitas (March 2006)Improve appearance: replace \/" and "/" Chapters: A1, A2.
² Paul Stokes, Program Chair, Computer and Electronics Engineering Technology, ITT Tech-
nical Institute, Houston, Tx (October 2004) Change (10012 = -810 + 710 = -110) to (10012 =
-810 + 110 = -110), CH2, Binary Arithmetic
² Paul Stokes, Program Chair Computer and Electronics Engineering Technology, ITT Tech-
nical Institute, Houston, Tx (October 2004) Near "Fold up the corners" change Out=B'C' to
Out=B'D', 14118.eps same change, Karnaugh Mapping
² The students of Bellingham Technical College's Instrumentation program, .
² Roger Hollingsworth (May 2003) Suggested a way to make the PLC motor control system
fail-safe.
² Jan-Willem Rensman (May 2002) Suggested the inclusion of Schmitt triggers and gate
hysteresis to the "Logic Gates" chapter.
² Don Stalkowski (June 2002) Technical help with PostScript-to-PDF ¯le format conversion.
² Joseph Teichman (June 2002) Suggestion and technical help regarding use of PNG images
instead of JPEG.
² MWalden@allaboutcircuits.com (June 2007) \Karnaugh Mapping", Larger Karnaugh Maps,
error: s/A'B'D/A'B'D'/.
456 APPENDIX A-2. CONTRIBUTOR LIST
Appendix A-3
DESIGN SCIENCE LICENSE
Copyright °c 1999-2000 Michael Stutz stutz@dsl.org
Verbatim copying of this document is permitted, in any medium.
A-3.1 0. Preamble
Copyright law gives certain exclusive rights to the author of a work, including the rights to copy,
modify and distribute the work (the "reproductive," "adaptative," and "distribution" rights).
The idea of "copyleft" is to willfully revoke the exclusivity of those rights under certain terms
and conditions, so that anyone can copy and distribute the work or properly attributed derivative
works, while all copies remain under the same terms and conditions as the original.
The intent of this license is to be a general "copyleft" that can be applied to any kind of work
that has protection under copyright. This license states those certain conditions under which a work
published under its terms may be copied, distributed, and modi¯ed.
Whereas "design science" is a strategy for the development of artifacts as a way to reform the
environment (not people) and subsequently improve the universal standard of living, this Design
Science License was written and deployed as a strategy for promoting the progress of science and
art through reform of the environment.
A-3.2 1. De¯nitions
"License" shall mean this Design Science License. The License applies to any work which contains
a notice placed by the work's copyright holder stating that it is published under the terms of this
Design Science License.
"Work" shall mean such an aforementioned work. The License also applies to the output of
the Work, only if said output constitutes a "derivative work" of the licensed Work as de¯ned by
copyright law.
"Object Form" shall mean an executable or performable form of the Work, being an embodiment
of the Work in some tangible medium.
457
458 APPENDIX A-3. DESIGN SCIENCE LICENSE
"Source Data" shall mean the origin of the Object Form, being the entire, machine-readable,
preferred form of the Work for copying and for human modi¯cation (usually the language, encoding
or format in which composed or recorded by the Author); plus any accompanying ¯les, scripts or
other data necessary for installation, con¯guration or compilation of the Work.
(Examples of "Source Data" include, but are not limited to, the following: if the Work is an
image ¯le composed and edited in 'PNG' format, then the original PNG source ¯le is the Source
Data; if the Work is an MPEG 1.0 layer 3 digital audio recording made from a 'WAV' format audio
¯le recording of an analog source, then the original WAV ¯le is the Source Data; if the Work was
composed as an unformatted plaintext ¯le, then that ¯le is the the Source Data; if the Work was
composed in LaTeX, the LaTeX ¯le(s) and any image ¯les and/or custom macros necessary for
compilation constitute the Source Data.)
"Author" shall mean the copyright holder(s) of the Work.
The individual licensees are referred to as "you."
A-3.3 2. Rights and copyright
The Work is copyright the Author. All rights to the Work are reserved by the Author, except
as speci¯cally described below. This License describes the terms and conditions under which the
Author permits you to copy, distribute and modify copies of the Work.
In addition, you may refer to the Work, talk about it, and (as dictated by "fair use") quote from
it, just as you would any copyrighted material under copyright law.
Your right to operate, perform, read or otherwise interpret and/or execute the Work is unre-
stricted; however, you do so at your own risk, because the Work comes WITHOUT ANY WAR-
RANTY { see Section 7 ("NO WARRANTY") below.
A-3.4 3. Copying and distribution
Permission is granted to distribute, publish or otherwise present verbatim copies of the entire Source
Data of the Work, in any medium, provided that full copyright notice and disclaimer of warranty,
where applicable, is conspicuously published on all copies, and a copy of this License is distributed
along with the Work.
Permission is granted to distribute, publish or otherwise present copies of the Object Form of
the Work, in any medium, under the terms for distribution of Source Data above and also provided
that one of the following additional conditions are met:
(a) The Source Data is included in the same distribution, distributed under the terms of this
License; or
(b) A written o®er is included with the distribution, valid for at least three years or for as long
as the distribution is in print (whichever is longer), with a publicly-accessible address (such as a
URL on the Internet) where, for a charge not greater than transportation and media costs, anyone
may receive a copy of the Source Data of the Work distributed according to the section above; or
(c) A third party's written o®er for obtaining the Source Data at no cost, as described in para-
graph (b) above, is included with the distribution. This option is valid only if you are a non-
commercial party, and only if you received the Object Form of the Work along with such an o®er.